Abstract: A method for detecting physical attacks on a computing device includes embedding a sensor or FPGA (Field Programmable Gate Array) on a circuit board for gathering a frequency response of a power distribution network providing power to the circuit board. During operation of the circuit board, the sensor identifies and gathers a frequency response suspected of resulting from a tamper effort, and compares the identified frequency response to a frequency response of tempering events. Based on the comparison, a determination of tampering is made.

Abstract: The present invention is directed to a method for verifying the integrity and authenticity of a printed circuit board, including associated components and packaging. The method is based on analyzing the power integrity of the power distribution network of the printed circuit board by measuring the S-parameter for the printed circuit board. Any tampering or counterfeiting can be determined by comparison of the S-parameter data or signature to a known authentic signature.

Abstract: A method for detecting physical attacks on a computing device includes embedding a sensor or FPGA (Field Programmable Gate Array) on a circuit board for gathering a frequency response of a power distribution network providing power to the circuit board. During operation of the circuit board, the sensor identifies and gathers a frequency response suspected of resulting from a tamper effort, and compares the identified frequency response to a frequency response of tempering events. Based on the comparison, a determination of tampering is made.

Abstract: A radio-frequency-identification (RFID) system includes an RFID tag and an RFID reader, where the RFID reader is configured to communicate with the RFID tag using time-hopped pulse-position modulation and ultra-wideband modulation. The time-hopped pulse-position modulation includes sending from the RFID tag to the RFID reader a series of pulses in time slots selected by the RFID tag through a cryptographically secure pseudo-random generator.

Abstract: A secure embedded system that uses cryptographic and biometric signal processing acceleration is described. In one embodiment, the secure embedded system is configured as a wireless pay-point protocol for brick-and-mortar and e-commerce applications in which biometric information is localized and does not require transmission of biometric data for authentication. In one embodiment, a key-generation function uses a dynamic key generator and static biometric components. In one embodiment, an embedded system design methodology provides hardware and software acceleration transparency.

Abstract: The invention relates to methods and apparatus suitable for executing a service or application at a client peer or client side, having a client specific device or client specific platform, with a reconfigurable architecture, said service or application being provided from a service peer or a service side. In a first aspect of the invention, the method comprises transmitting to the client peer from the server peer an abstract bytecode. The abstract bytecode is generated at the service peer by performing a compilation of an application. The abstract bytecode includes hardware bytecode and software bytecode. At the client peer, the abstract bytecode is transformed into native bytecode for the client specific device.

Abstract: A method for designing an electronic system having at least one digital part. The method includes representing a behavioral description of the system as a first set of objects with a first set of relations therebetween. Furthermore, the method includes refining said behavioral description into an implementable description of said system, said implementable description being represented as a second set of objects with a second set of relations therebetween. Also, the method includes retaining at least one of said second objects for reuse in the design of a second electronic system.

Abstract: The present invention is a design apparatus compiled on a computer environment for generating from a behavioral description of a system comprising at least one digital system part, an implementable description for said system, said behavioral description being represented on said computer environment as a first set of objects with a first set of relations therebetween, said implementable description being represented on said computer environment as a second set of objects with a second set of relations therebetween, said first and second set of objects being part of a design environment.

Abstract: The present invention is a design apparatus compiled on a computer environment for generating from a behavioral description of a system comprising at least one digital system part, an implementable description for said system, said behavioral description being represented on said computer environment as a first set of objects with a first set of relations therebetween, said implementable description being represented on said computer environment as a second set of objects with a second set of relations therebetween, said first and second set of objects being part of a design environment.

Abstract: The present invention relates to a receiver at the head-end or a centralizing unit side in a communications system or network for signals in the upstream direction which is the direction from user to head-end or a centralizing unit that is linked to a number of users, the number being equal to or larger than one.

Abstract: The present invention is a design apparatus compiled on a computer environment for generating from a behavioral description of a system comprising at least one digital system part, an implementable description for said system, said behavioral description being represented on said computer environment as a first set of objects with a first set of relations therebetween, said implementable description being represented on said computer environment as a second set of objects with a second set of relations therebetween, said first and second set of objects being part of a design environment.

Abstract: A receiver is disclosed at the head-end or a centralizing unit side in a communications system or network for signals in the upstream direction which is the direction from user to head-end or a centralizing unit that is linked to a number of users, the number being equal to or larger than one. The receiver is suited for the reception of burst mode signals. The receiver performs a channel estimation on a per-burst basis in real time or essentially immediate. The channel estimation is necessary to do successful data detection of modulated data. The receiver of the invention performs the channel estimation and data detection in one compact all-digital mechanism that has no tuning parts. The reception method works in an aspect according to the principle of a matched filter receiver, but stores no local copy of the required matched waveform. Rather, a copy of the matched waveform is included in the preamble of the signals.

Abstract: The invention relates to methods and apparatus suitable for executing a service or application at a client peer or client side, having a client specific device or client specific platform, with a reconfigurable architecture, said service or application being provided from a service peer or a service side. In a first aspect of the invention, the method comprises transmitting to the client peer from the server peer an abstract bytecode. The abstract bytecode is generated at the service peer by performing a compilation of an application. The abstract bytecode includes hardware bytecode and software bytecode. At the client peer, the abstract bytecode is transformed into native bytecode for the client specific device.

Abstract: The present invention is a design apparatus compiled on a computer environment for generating from a behavioral description of a system comprising at least one digital system part, an implementable description for said system, said behavioral description being represented on said computer environment as a first set of objects with a first set of relations therebetween, said implementable description being represented on said computer environment as a second set of objects with a second set of relations therebetween, said first and second set of objects being part of a design environment.