Abstract: Embodiments herein describe a hardware accelerator with an array of data processing engines (DPEs) which includes a controller (e.g., a microcontroller) for multiple columns of the array. The controllers can be hardened circuitry that executes software code (or firmware) that controls the hardware accelerator. In one embodiment, the task of the controller is to control and orchestrate the functions performed by the hardware accelerator.

Abstract: Examples herein describe an array of controllers. The array includes a first controller having a first memory and a first processor and a second controller having a second memory and a second processor. The first controller is configured to execute a first segment of control code. The control code is compiled based on one or more instructions included in a user defined application. The second controller is configured to execute a second segment of the control code. The one or more instructions included in the user defined application are executable by executing the first segment of the control code and the second segment of the control code.

Abstract: Embodiments herein describe a hardware accelerator with an array of data processing engines (DPEs) which includes a controller (e.g., a microcontroller) for multiple columns of the array. The controllers can be hardened circuitry that executes software code (or firmware) that controls the hardware accelerator. In one embodiment, the task of the controller is to control and orchestrate the functions performed by the hardware accelerator.

Abstract: Embodiments herein describe using DMA circuitry in multiple tiles in a hardware accelerator array to program the DMA operations within the array. For example, a system on a chip (SoC) may include a controller that is external to the hardware accelerator array. While the controller can be used to program the DMA circuitry within the array, this can be slow since the controller may be compute limited. Instead, the embodiments herein describe techniques where the controller is provided pointers to the register read and write corresponding to the DMA operations. The controller can provide these pointers to multiple DMA engines in the hardware accelerator array (e.g., DMA circuitry in interface tiles) which fetch the DMA operations and program themselves, as well as other DMA circuitry in the array.

Abstract: An industrial monitoring system comprises a plurality of gateways in transmission range of a monitoring device. A gateway, of the plurality of gateways, receives a first transmission indicating that the monitoring device is requesting to communicate with any one of the plurality of gateways. The gateway determines a signal quality of the received first transmission, and determines a wait time in which at least a portion of the wait time is inversely proportional to the signal quality. After expiration of the wait period, the gateway devices sends, to the monitoring device a second transmission indicating acceptance of the request.