Abstract: A system including an embedded logic analyzer block having an input receiving a plurality of signals from a system under test, and a trigger event block detecting an occurrence of an event based in part upon the plurality of signals. The system further includes a block with a first input receiving one or more of the plurality of signals, a second input receiving a signal based upon the detection of the occurrence of the event, circuitry generating a distinct set test signals based on the signals at the first input and second input of the block, the distinct set of test signals being different from the plurality of signals appearing at the input of the embedded logic analyzer block, and an output providing the generated distinct set of test signals to the embedded logic analyzer block as additional test signals for at least one of sampling thereof and event triggering.

Abstract: A system for testing or debugging a device under test having an embedded logic analyzer. In one embodiment, the system includes software stored in non-transitory memory for testing a device under test having an embedded logic analyzer, the software program product having instructions which, when executed by a computing device associated with the device under test cause the computing device to reconstruct signals of interest in the device under test based at least in part upon signals captured by the embedded logic analyzer during the test or debug session, and cause the computing device to display the reconstructed signals of interest to a user of the computing device.

Abstract: An integrated circuit including a logic analyzer with enhanced analyzing and debugging capabilities and a method therefore. In one embodiment, an integrated circuit includes a logic analyzer having a first input receiving a plurality of signals and an output for providing an indication of a detection, by the logic analyzer, of at least one trigger event; and a built in self test block having a first input for receiving one or more of the signals appearing at the first input of the logic analyzer, a second input coupled to the output of the logic analyzer for selectively enabling the BIST block, the BIST block generating and maintaining a signature based upon the first and second inputs thereof.

Abstract: Disclosed is a method for tuning control signals associated with one or more memory devices. The method includes performing a number of memory access operations on at least one memory device and recording results of the memory access operations. Specifically, the memory access operations are performed with different time delays for a first edge of a control signal. The control signal used for capturing data is provided by the at least one memory device. The method further includes selecting a time delay from the time delays used in the memory access operations. Moreover, the method includes utilizing the selected time delay in performing subsequent memory access operations on the at least one memory device. Also disclosed is a system including at least one memory device and an integrated circuit operatively coupled to the at least one memory device. The system incorporates the method for tuning control signals.

Abstract: A system for testing or debugging a device under test having an embedded logic analyzer. In one embodiment, the system includes software stored in non-transitory memory for testing a device under test having an embedded logic analyzer, the software program product having instructions which, when executed by a computing device associated with the device under test cause the computing device to reconstruct signals of interest in the device under test based at least in part upon signals captured by the embedded logic analyzer during the test or debug session, and cause the computing device to display the reconstructed signals of interest to a user of the computing device.

Abstract: An integrated circuit including a logic analyzer with enhanced analyzing and debugging capabilities and a method therefor. In one embodiment, an integrated circuit includes a logic analyzer having a first input receiving a plurality of signals and an output for providing an indication of a detection, by the logic analyzer, of at least one trigger event; and a built in self test block having a first input for receiving one or more of the signals appearing at the first input of the logic analyzer, a second input coupled to the output of the logic analyzer for selectively enabling the BIST block, the BIST block generating and maintaining a signature based upon the first and second inputs thereof.

Abstract: Disclosed is a method for tuning control signals associated with one or more memory devices. The method includes performing a number of memory access operations on at least one memory device and recording results of the memory access operations. Specifically, the memory access operations are performed with different time delays for a first edge of a control signal. The control signal used for capturing data is provided by the at least one memory device. The method further includes selecting a time delay from the time delays used in the memory access operations. Moreover, the method includes utilizing the selected time delay in performing subsequent memory access operations on the at least one memory device. Also disclosed is a system including at least one memory device and an integrated circuit operatively coupled to the at least one memory device. The system incorporates the method for tuning control signals.

Abstract: An automated, Web-based system and method for rating a candidate for employment, wherein an application and/or resume are submitted electronically and are subjected to an automated review process, wherein the applicant's qualifications may be first rated against a minimal, pre-selected set of employment criteria, and wherein the application, if it passes the initial screen, is subsequently screened against a more robust, pre-selected set of rating criteria to determine qualification for a particular position or set of positions. The invention also includes the ability to automate the scoring and rating of written narrative responses provided by job applicants, wherein the computerized method implements preselected methods of obtaining consensus, if required, between individual raters and then applies the scores in a predefined manner to obtain a final rating for the applicant.