Abstract: Disclosed herein are integrated circuit (IC) structures fabricated with selective cap deposition techniques on graphene-capped conductive lines and IC structures and devices with graphene on capped conductive lines. In one example, an IC structure includes an interconnect layer with a conductive line, a conductive cap layer over the conductive line, and a layer of graphene between the conductive line and the conductive cap or a layer of graphene over the conductive cap. In one such example, the layer of graphene may enable lower resistance in the conductive line and the conductive cap may improve electromigration reliability.

Abstract: A method includes depositing a layer of silicon oxide onto a layer of silicon carbide; ion implanting the layer of silicon carbide, annealing the ion implanted layer of silicon carbide to produce defects within the layer of silicon carbide, performing photolithography using a mask layer on regions of the layer of silicon carbide to define regions for electrode deposition, removing the layer of silicon oxide from the layer of silicon carbide in the one or more regions for electrode deposition, forming one or more electrodes by depositing indium tin oxide (ITO) in each of the regions for electrode deposition, performing a first lift-off operation to remove the mask layer surrounding the electrodes, depositing a passivation and gate silicon oxide layer on top of the layer of silicon carbide and the electrodes, and performing a second lift-off operation to fabricate an optically transparent ITO gate between the electrodes.