Abstract: A method and apparatus for performing memory access operations during a memory relocation in a computing system are disclosed. In response to initiating a relocation operation from a source region of memory to a destination region of memory, copying one or more lines of the source region to the destination region, and activating a mirror operation mode in a communication circuit coupled to one or more devices included in the computing system. In response to receiving an access request from a device, reading previously stored data from the source region, and in response to determining the access request includes a write request, storing new data included in the write request to locations in both the source and destination regions.

Abstract: A method and apparatus for performing memory access operations during a memory relocation in a computing system are disclosed. In response to initiating a relocation operation from a source region of memory to a destination region of memory, copying one or more lines of the source region to the destination region, and activating a mirror operation mode in a communication circuit coupled to one or more devices included in the computing system. In response to receiving an access request from a device, reading previously stored data from the source region, and in response to determining the access request includes a write request, storing new data included in the write request to locations in both the source and destination regions.

Abstract: A method and apparatus for performing memory access operations during a memory relocation in a computing system are disclosed. In response to initiating a relocation operation from a source region of memory to a destination region of memory, copying one or more lines of the source region to the destination region, and activating a mirror operation mode in a communication circuit coupled to one or more devices included in the computing system. In response to receiving an access request from a device, reading previously stored data from the source region, and in response to determining the access request includes a write request, storing new data included in the write request to locations in both the source and destination regions.

Abstract: Embodiments of input/output hub unit are disclosed for aggregating interrupts received from multiple endpoint devices. The input/output hub may include an interface unit and one or more communication units. Each communication unit may be configured to receive messages from a corresponding endpoint device. The interface unit may be configured to update a first pointer within a first data structure responsive to a request from a given one of the communication units. The interface unit may be further configured to stored data in a second data structure responsive to updating the first pointer, reading a second pointer and the first pointer, and sending an interrupt responsive to a determination that the first and second pointers are equal.

Abstract: Embodiments of input/output hub unit are disclosed for aggregating interrupts received from multiple endpoint devices. The input/output hub may include an interface unit and one or more communication units. Each communication unit may be configured to receive messages from a corresponding endpoint device. The interface unit may be configured to update a first pointer within a first data structure responsive to a request from a given one of the communication units. The interface unit may be further configured to stored data in a second data structure responsive to updating the first pointer, reading a second pointer and the first pointer, and sending an interrupt responsive to a determination that the first and second pointers are equal.

Abstract: A method and apparatus for performing memory access operations during a memory relocation in a computing system are disclosed. In response to initiating a relocation operation from a source region of memory to a destination region of memory, copying one or more lines of the source region to the destination region, and activating a mirror operation mode in a communication circuit coupled to one or more devices included in the computing system. In response to receiving an access request from a device, reading previously stored data from the source region, and in response to determining the access request includes a write request, storing new data included in the write request to locations in both the source and destination regions.

Abstract: Embodiments of input/output hub unit are disclosed for aggregating interrupts received from multiple endpoint devices. The input/output hub may include an interface unit and one or more communication units. Each communication unit may be configured to receive messages from a corresponding endpoint device. The interface unit may be configured to update a first pointer within a first data structure responsive to a request from a given one of the communication units. The interface unit may be further configured to stored data in a second data structure responsive to updating the first pointer, reading a second pointer and the first pointer, and sending an interrupt responsive to a determination that the first and second pointers are equal.

Abstract: Embodiments of input/output hub unit are disclosed for aggregating interrupts received from multiple endpoint devices. The input/output hub may include an interface unit and one or more communication units. Each communication unit may be configured to receive messages from a corresponding endpoint device. The interface unit may be configured to update a first pointer within a first data structure responsive to a request from a given one of the communication units. The interface unit may be further configured to stored data in a second data structure responsive to updating the first pointer, reading a second pointer and the first pointer, and sending an interrupt responsive to a determination that the first and second pointers are equal.

Abstract: Embodiments of input/output hub unit are disclosed for aggregating interrupts received from multiple endpoint devices. The input/output hub may include an interface unit and one or more communication units. Each communication unit may be configured to receive messages from a corresponding endpoint device. The interface unit may be configured to update a first pointer within a first data structure responsive to a request from a given one of the communication units. The interface unit may be further configured to stored data in a second data structure responsive to updating the first pointer, reading a second pointer and the first pointer, and sending an interrupt responsive to a determination that the first and second pointers are equal.

Abstract: An input/output hub may include an interface unit and one or more communication units. Each communication unit may be configured to receive interrupts or messages from a corresponding endpoint device. A given communication unit may be further configured to synthesize a virtual address from the received message, translate the synthesized virtual address to a real address, and then translate the real address to a physical address. The interface unit may be configured to send an interrupt dependent upon the physical address.

Abstract: A system may include a processor which may include a cache memory and a Direct Memory Access (DMA) controller, a peripheral device on an I/O expansion bus, and a bus interface coupled to the I/O expansion bus and the processor. The bus controller may determine if data packets sent from the peripheral device to the processor include a DMA write instruction to the cache memory with an optional desired cache location. Upon determining a DMA write instruction to the cache memory is included in the data packet, the bus controller may format the data in the data packet for storage in the cache and either receive the desired cache location or determine an appropriate location within the cache to store the formatted data. The bus controller may determine an alternate location within the cache if the desired location within the cache cannot accept more data from the peripheral device.

Abstract: Embodiments of input/output hub unit are disclosed for virutalizing an input/output subsystem. The input/output hub may include an interface unit and one or more communication units. Each communication unit may be configured to receive interrups or messages from a corresponding endpoint device. A given communication unit may be further configured to synthesize a virtual address from the received message, translate the synthesized virtual address to a real address, and then translate the real address to a physical address. The interface unit may be configured to send an interrupt dependent upon the physical address.

Abstract: Embodiments of input/output hub unit are disclosed for aggregating interrupts received from multiple endpoint devices. The input/output hub may include an interface unit and one or more communication units. Each communication unit may be configured to receive messages from a corresponding endpoint device. The interface unit may be configured to update a first pointer within a first data structure responsive to a request from a given one of the communication units. The interface unit may be further configured to stored data in a second data structure responsive to updating the first pointer, reading a second pointer and the first pointer, and sending an interrupt responsive to a determination that the first and second pointers are equal.

Abstract: A system may include a processor which may include a cache memory and a Direct Memory Access (DMA) controller, a peripheral device on an I/O expansion bus, and a bus interface coupled to the I/O expansion bus and the processor. The bus controller may determine if data packets sent from the peripheral device to the processor include a DMA write instruction to the cache memory with an optional desired cache location. Upon determining a DMA write instruction to the cache memory is included in the data packet, the bus controller may format the data in the data packet for storage in the cache and either receive the desired cache location or determine an appropriate location within the cache to store the formatted data. The bus controller may determine an alternate location within the cache if the desired location within the cache cannot accept more data from the peripheral device.