Patents by Inventor Patrick T. Bever

Patrick T. Bever has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7255360
    Abstract: A rider support assembly for a bicycle, motorcycle or other multi-wheeled vehicle that utilizes a harness to suspend the rider from a support frame that is attached to a ball-type mounting structure. The support harness includes straps or a sling that is secured to the rider's torso and/or legs. A base section of the support frame includes a connecting structure (e.g., a socket) that is movably connects to and supported by the mounting structure such that the support frame can be pivoted in any direction by the rider during operation. A flexible spine extends upward along the rider's back and is secured to the rider's upper body by the support harness. An optional mounting structure pivots relative to the vehicle to facilitate a relatively stiff spine that supports the rider when sitting upright or leaning back.
    Type: Grant
    Filed: January 18, 2005
    Date of Patent: August 14, 2007
    Inventor: Patrick T. Bever
  • Patent number: 6363019
    Abstract: A programmable logic device (PLD) including a non-volatile memory array for persistently storing configuration data, and a volatile memory array for temporarily storing the configuration data and controlling the various logic resources of the PLD to perform a user's logic operation. When the PLD is reset, an addressing circuit causes a column of non-volatile memory cells to transmit configuration data values to a corresponding column of volatile memory cells on a series of write lines. To verify that a configuration data value is successfully written from each non-volatile memory cell to a corresponding volatile memory cell, the data value transmitted on each write line is compared with the stored data value transmitted from each volatile memory cell on a corresponding read line.
    Type: Grant
    Filed: November 3, 2000
    Date of Patent: March 26, 2002
    Assignee: Xilinx, Inc.
    Inventors: Brian D. Erickson, Barry Wong, Patrick T. Bever