Abstract: A complementary metal-oxide semiconductor (CMOS) compatible radio frequency (RF) switch circuit and high voltage control circuit (HVCC) are disclosed. In a mobile device, an RF switch circuit couples a first RF circuit to a shared antenna through a low resistance path while electrically isolating other RF circuits from the antenna by a high resistance path. Each path in the RF switch circuit includes a series metal-oxide semiconductor (MOS) Field-Effect Transistor (FET) MOSFET switch which provides a low resistance path when fully turned on by a strong positive gate-to-source voltage and a corresponding body bias voltage, and a high resistance path when fully turned off by a strong negative gate-to-source voltage and corresponding body bias voltage. The RF switch circuit paths are controlled by a CMOS compatible HVCC which supplies high and low voltage signals to the gate node and body bias node of each MOSFET in each path.

Abstract: A complementary metal-oxide semiconductor (CMOS) compatible radio frequency (RF) switch circuit and high voltage control circuit (HVCC) are disclosed. In a mobile device, an RF switch circuit couples a first RF circuit to a shared antenna through a low resistance path while electrically isolating other RF circuits from the antenna by a high resistance path. Each path in the RF switch circuit includes a series metal-oxide semiconductor (MOS) Field-Effect Transistor (FET) MOSFET switch which provides a low resistance path when fully turned on by a strong positive gate-to-source voltage and a corresponding body bias voltage, and a high resistance path when fully turned off by a strong negative gate-to-source voltage and corresponding body bias voltage. The RF switch circuit paths are controlled by a CMOS compatible HVCC which supplies high and low voltage signals to the gate node and body bias node of each MOSFET in each path.

Abstract: Embodiments provide a clock generation circuit with a first phase-locked loop (PLL) and a second PLL that are coupled in parallel with one another and receive a same feedback signal. The first and second PLLs generate respective output signals that are combined to generate an output clock signal. A version of the output clock signal may be passed back to the first and second PLLs as the feedback signal. In some embodiments, the second PLL may include a switch to selectively close the second PLL after the first PLL has locked. In some embodiments, the second PLL may include a bulk acoustic wave (BAW) voltage-controlled oscillator (VCO) and the first PLL may include a different type of VCO.

Abstract: Embodiments provide a clock generation circuit with a first phase-locked loop (PLL) and a second PLL that are coupled in parallel with one another and receive a same feedback signal. The first and second PLLs generate respective output signals that are combined to generate an output clock signal. A version of the output clock signal may be passed back to the first and second PLLs as the feedback signal. In some embodiments, the second PLL may include a switch to selectively close the second PLL after the first PLL has locked. In some embodiments, the second PLL may include a bulk acoustic wave (BAW) voltage-controlled oscillator (VCO) and the first PLL may include a different type of VCO.

Abstract: Embodiments of apparatuses, systems and methods relating to a mixer having high second- and third-order intercept points are disclosed. Other embodiments may be described and claimed.

Abstract: Embodiments of apparatuses, systems and methods relating to a mixer having high second- and third-order intercept points are disclosed. Other embodiments may be described and claimed.