Abstract: An exemplary cochlear implant system includes a sound processing assembly configured to be external to a patient and first and second extension members coupled to the sound processing assembly. The sound processing assembly includes a sound processing unit configured to process an audio signal and transmit one or more control parameters based on the audio signal to an implantable cochlear stimulator and a battery module configured to be electrically coupled to the sound processing unit and provide operating power to the sound processing unit. The first extension member has a distal portion configured to be coupled to a first ear of the patient and the second extension member has a distal portion configured to be coupled to a second ear of the patient. The first and second extension members typically extend back from the ears, thus positioning the sound processing assembly behind the patient's head.

Abstract: An exemplary method includes a sound processing unit 1) directing an implantable cochlear stimulator coupled to a plurality of electrodes to generate an electrical stimulation current in accordance with one or more stimulation parameters, 2) automatically detecting an impedance of at least one of the electrodes, and 3) directing, in accordance with the detected impedance, the implantable cochlear stimulator to adjust a pulse width of the electrical stimulation current to maintain constant a total electric charge level of the electrical stimulation current.

Abstract: An exemplary cochlear implant system includes a sound processing assembly configured to be external to a patient and first and second extension members coupled to the sound processing assembly. The sound processing assembly includes a sound processing unit configured to process an audio signal and transmit one or more control parameters based on the audio signal to an implantable cochlear stimulator and a battery module configured to be electrically coupled to the sound processing unit and provide operating power to the sound processing unit. The first extension member has a distal portion configured to be coupled to a first ear of the patient and the second extension member has a distal portion configured to be coupled to a second ear of the patient. The first and second extension members typically extend back from the ears, thus positioning the sound processing assembly behind the patient's head.

Abstract: An exemplary method includes a sound processing unit 1) directing an implantable cochlear stimulator coupled to a plurality of electrodes to generate an electrical stimulation current in accordance with one or more stimulation parameters, 2) automatically detecting an impedance of at least one of the electrodes, and 3) directing, in accordance with the detected impedance, the implantable cochlear stimulator to adjust a pulse width of the electrical stimulation current to maintain constant a total electric charge level of the electrical stimulation current.

Abstract: Methods and systems for automatically detecting an impedance of one or more electrodes in a cochlear implant system include providing an implantable cochlear stimulator coupled to one or more electrodes, generating an electrical stimulation current with the implantable cochlear stimulator in accordance with stimulation parameters, automatically detecting an impedance of at least one of the electrodes in accordance with a predefined schedule, and performing a predefined action in accordance with the detected impedance.

Abstract: A disc drive storage system and device for use with a host computer is provided in which information contained on the disc drive can be write protected with an ATA compatible write protection scheme. The system includes at least one rotatable disc having a disc surface with a plurality of physical memory locations referenced by the host computer through logical block addresses. The physical memory locations include data storage locations and attribute storage locations that store protection status information corresponding to the data storage locations. A disc controller receives write protection commands that are compatible with an ATA data exchange protocol from the host. These write protection commands relate to the write protection status information of at least one logical block address. The controller executes the write protection commands to thereby implement a write protection scheme compatible with the ATA data exchange protocol.

Abstract: A disc drive includes a base and a disc rotatably attached to the base. The disc drive also includes an actuator assembly rotatably attached to said base and a device for moving the actuator assembly. The disc drive includes servo circuitry and a controller for controlling movement of the actuator and head switches during track seek operations. The disc drive determines the average seek time for each head and also measures the amount of time for a head switch from the transducer head having the shortest average seek time to all the other transducing heads in the disc drive. When a seek is performed, the controller in the disc drive determines if the shortest average seek time plus the seek time from the transducing head to the transducing head on the surface containing the target track and sector is less than the average seek time of the head on the surface having the target track and sector.

Abstract: A disc drive storage system and device for use with a host computer is provided in which information contained on the disc drive can be write protected with an ATA compatible write protection scheme. The system includes at least one rotatable disc having a disc surface with a plurality of physical memory locations referenced by the host computer through logical block addresses. The physical memory locations include data storage locations and attribute storage locations that store protection status information corresponding to the data storage locations. A disc controller receives write protection commands that are compatible with an ATA data exchange protocol from the host. These write protection commands relate to the write protection status information of at least one logical block address. The controller executes the write protection commands to thereby implement a write protection scheme compatible with the ATA data exchange protocol.