Abstract: In described examples, a switching mode power supply includes an output filter, a driver, a pulse width modulator, and pulse adaptation circuitry. The output filter is configured to provide output of the switching mode power supply. The driver is coupled to the output filter and is configured to switch current to the output filter. The pulse width modulator is configured to generate pulses that control switching of current by the driver. The pulse width modulator includes spread spectrum logic configured to randomize timing of the pulses generated by the pulse width modulator. The pulse adaptation circuitry is configured to identify an instantaneous excursion of the output of the switching mode power supply beyond a predetermined threshold, and to modify the randomized timing of the pulses produced by the pulse width modulator based on the identified instantaneous excursion.

Abstract: In described examples, a switching mode power supply includes an output filter, a driver, a pulse width modulator, and pulse adaptation circuitry. The output filter is configured to provide output of the switching mode power supply. The driver is coupled to the output filter and is configured to switch current to the output filter. The pulse width modulator is configured to generate pulses that control switching of current by the driver. The pulse width modulator includes spread spectrum logic configured to randomize timing of the pulses generated by the pulse width modulator. The pulse adaptation circuitry is configured to identify an instantaneous excursion of the output of the switching mode power supply beyond a predetermined threshold, and to modify the randomized timing of the pulses produced by the pulse width modulator based on the identified instantaneous excursion.

Abstract: An ultra-fast drive circuit (40) providing a rail-to-rail drive voltage at an output node (N1). A pair of bipolar output transistors (Q3, Q4) are selectively driven via a FET drive circuit (42), and by a control circuit (44) to achieve a rail-to-rail output voltage (Vcc−Vee) that is very fast. The drive FETs comprise three serially connected FETs (M5, M6, M7) whereby the middle FET (M6) is the control FET effecting the control of the output transistors (Q3, Q4). The other two FETs (M5, M7) are always in the on state and complete either the pull-up or pull-down of the voltage at the output node (N1), depending on the state of the middle FET (M6). The control FETs (44) provide two output control signals (46, 48) to the output transistors (Q3, Q4), with the control line (48) controlling the state of the middle switching FET (M6).

Abstract: An ultra-fast drive circuit (40) providing a rail-to-rail drive voltage at an output node (N1). A pair of bipolar output transistors (Q3, Q4) are selectively driven via a FET drive circuit (42), and by a control circuit (44) to achieve a rail-to-rail output voltage (Vcc-Vee) that is very fast. The drive FETs comprise three serially connected FETs (M5, M6, M7) whereby the middle FET (M6) is the control FET effecting the control of the output transistors (Q3, Q4). The other two FETs (M5, M7) are always in the on state and complete either the pull-up or pull-down of the voltage at the output node (N1), depending on the state of the middle FET (M6). The control FETs (44) provide two output control signals (46, 48) to the output transistors (Q3, Q4), with the control line (48) controlling the state of the middle switching FET (M6).

Abstract: A HDD write driver circuit (30) having two sets of boost devices (Q1, M2, and Q2, M1) which are temporarily turned on during a current reversal to boost the normal current and increase the differential transient voltage across the coil (LS) while decreasing the TRTF. During a current reversal cycle, one set of transistors is turned on while the other set is left off. The on set to pulls the node at one end of the coil substantially to the positive rail, and pulls the other node at the other end of the coil substantially to the lower rail (Vee). The boost FETs (M1, M2) are preferably large PMOS devices that must be driven hard to achieve a quick transient switching time. Advantageously, when one of the PMOS FETs (M1, M2) are on, the associated series resistor (RS) is bypassed.