Patents by Inventor Patrick van Cleemput

Patrick van Cleemput has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180044790
    Abstract: A method for performing atomic layer deposition (ALD) on a substrate is provided, including: exposing the substrate to a first reactant and an additive simultaneously, the first reactant and the additive being configured to adsorb on exposed surfaces of the substrate, a partial pressure of the additive being configured so that adsorption of the additive in a gap feature of the substrate decreases as depth increases in the gap feature; after exposing the substrate to the first reactant and the additive, exposing the substrate to a second reactant, the second reactant configured to react with the adsorbed first reactant to form a thin film product, the second reactant configured to react with the adsorbed additive to remove the adsorbed additive from the substrate surface.
    Type: Application
    Filed: August 12, 2016
    Publication date: February 15, 2018
    Inventor: Patrick Van Cleemput
  • Patent number: 9875968
    Abstract: A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: January 23, 2018
    Assignee: Lam Research Corporation
    Inventors: Artur Kolics, William T. Lee, Larry Zhao, Derek Wong, Praveen Nalla, Kaihan Ashtiani, Patrick A. Van Cleemput, Yezdi Dordi
  • Publication number: 20180012759
    Abstract: Thin tin oxide films are used as spacers in semiconductor device manufacturing. In one implementation, thin tin oxide film is conformally deposited onto a semiconductor substrate having an exposed layer of a first material (e.g., silicon oxide or silicon nitride) and a plurality of protruding features comprising a second material (e.g., silicon or carbon). For example, 10-100 nm thick tin oxide layer can be deposited using atomic layer deposition. Next, tin oxide film is removed from horizontal surfaces, without being completely removed from the sidewalls of the protruding features. Next, the material of protruding features is etched away, leaving tin oxide spacers on the substrate. This is followed by etching the unprotected portions of the first material, without removal of the spacers. Next, underlying layer is etched, and spacers are removed. Tin-containing particles can be removed from processing chambers by converting them to volatile tin hydride.
    Type: Application
    Filed: September 22, 2017
    Publication date: January 11, 2018
    Inventors: David Charles Smith, Richard Wise, Arpan Mahorowala, Patrick A. Van Cleemput, Bart J. van Schravendijk
  • Publication number: 20180005801
    Abstract: Provided are apparatuses and methods for performing deposition and etch processes in an integrated tool. An apparatus may include a plasma processing chamber that is a capacitively-coupled plasma reactor, and the plasma processing chamber can include a showerhead that includes a top electrode and a pedestal that includes a bottom electrode. The apparatus may be configured with an RF hardware configuration so that an RF generator may power the top electrode in a deposition mode and power the bottom electrode in an etch mode. In some implementations, the apparatus can include one or more switches so that at least an HFRF generator is electrically connected to the showerhead in a deposition mode, and the HFRF generator and an LFRF generator is electrically connected to the pedestal and the showerhead is grounded in the etch mode.
    Type: Application
    Filed: August 22, 2017
    Publication date: January 4, 2018
    Inventors: Akhil Singhal, Patrick A. Van Cleemput, Martin E. Freeborn, Bart J. van Schravendijk
  • Patent number: 9824893
    Abstract: Thin tin oxide films are used as spacers in semiconductor device manufacturing. In one implementation, thin tin oxide film is conformally deposited onto a semiconductor substrate having an exposed layer of a first material (e.g., silicon oxide or silicon nitride) and a plurality of protruding features comprising a second material (e.g., silicon or carbon). For example, 10-100 nm thick tin oxide layer can be deposited using atomic layer deposition. Next, tin oxide film is removed from horizontal surfaces, without being completely removed from the sidewalls of the protruding features. Next, the material of protruding features is etched away, leaving tin oxide spacers on the substrate. This is followed by etching the unprotected portions of the first material, without removal of the spacers. Next, underlying layer is etched, and spacers are removed. Tin-containing particles can be removed from processing chambers by converting them to volatile tin hydride.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: November 21, 2017
    Assignee: Lam Research Corporation
    Inventors: David Charles Smith, Richard Wise, Arpan Mahorowala, Patrick A. Van Cleemput, Bart J. van Schravendijk
  • Patent number: 9773643
    Abstract: Provided are apparatuses and methods for performing deposition and etch processes in an integrated tool. An apparatus may include a plasma processing chamber that is a capacitively-coupled plasma reactor, and the plasma processing chamber can include a showerhead that includes a top electrode and a pedestal that includes a bottom electrode. The apparatus may be configured with an RF hardware configuration so that an RF generator may power the top electrode in a deposition mode and power the bottom electrode in an etch mode. In some implementations, the apparatus can include one or more switches so that at least an HFRF generator is electrically connected to the showerhead in a deposition mode, and the HFRF generator and an LFRF generator is electrically connected to the pedestal and the showerhead is grounded in the etch mode.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: September 26, 2017
    Assignee: Lam Research Corporation
    Inventors: Akhil Singhal, Patrick A. Van Cleemput, Martin E. Freeborn, Bart J. van Schravendijk
  • Publication number: 20170162512
    Abstract: A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.
    Type: Application
    Filed: February 24, 2017
    Publication date: June 8, 2017
    Inventors: Artur Kolics, William T. Lee, Larry Zhao, Derek Wong, Praveen Nalla, Kaihan Ashtiani, Patrick A. Van Cleemput, Yezdi Dordi
  • Publication number: 20170140931
    Abstract: Provided are methods and apparatus for ultraviolet (UV) assisted capillary condensation to form dielectric materials. In some embodiments, a UV driven reaction facilitates photo-polymerization of a liquid phase flowable material. Applications include high quality gap fill in high aspect ratio structures and por sealing of a porous solid dielectric film. According to various embodiments, single station and multi-station chambers configured for capillary condensation and UV exposure are provided.
    Type: Application
    Filed: November 16, 2015
    Publication date: May 18, 2017
    Inventors: Patrick A. Van Cleemput, Nicholas Muga Ndiege
  • Publication number: 20170137943
    Abstract: Provided are methods and apparatus for ultraviolet (UV) assisted capillary condensation to form dielectric materials. In some embodiments, a UV driven reaction facilitates photo-polymerization of a liquid phase flowable material. Applications include high quality gap fill in high aspect ratio structures and por sealing of a porous solid dielectric film. According to various embodiments, single station and multi-station chambers configured for capillary condensation and UV exposure are provided.
    Type: Application
    Filed: November 16, 2015
    Publication date: May 18, 2017
    Inventors: Jonathan D. Mohn, Nicholas Muga Ndiege, Patrick A. Van Cleemput, David Fang Wei Chen, Wenbo Liang, Shawn M. Hamilton
  • Patent number: 9583386
    Abstract: A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: February 28, 2017
    Assignee: Lam Research Corporation
    Inventors: Artur Kolics, William T. Lee, Larry Zhao, Derek Wong, Praveen Nalla, Kaihan Ashtiani, Patrick A. Van Cleemput, Yezdi Dordi
  • Publication number: 20160329213
    Abstract: A method for providing a metal diffusion barrier layer comprising providing a substrate including a metal layer; depositing a dielectric layer on the metal layer; defining a feature in the dielectric layer, wherein the feature includes side walls defined by the dielectric layer and a bottom surface defined by the metal layer; selectively depositing a metal diffusion barrier layer on the side walls of the feature and not depositing the metal diffusion barrier layer on the bottom surface of the feature, wherein the metal diffusion barrier layer includes amorphous carbon; and depositing metal in the feature.
    Type: Application
    Filed: April 11, 2016
    Publication date: November 10, 2016
    Inventors: Wei Tang, Jason Daejin Park, Patrick A. Van Cleemput, Yezdi Dordi
  • Publication number: 20160118296
    Abstract: A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.
    Type: Application
    Filed: October 2, 2015
    Publication date: April 28, 2016
    Inventors: Artur Kolics, William T. Lee, Larry Zhao, Derek Wong, Praveen Nalla, Kaihan Ashtiani, Patrick A. Van Cleemput, Yezdi Dordi
  • Publication number: 20160056071
    Abstract: Implementations of the methods and apparatus disclosed herein relate to pore sealing of porous dielectric films using flowable dielectric material. The methods involve exposing a substrate having an exposed porous dielectric film thereon to a vapor phase dielectric precursor under conditions such that a flowable dielectric material selectively deposits in the pores of the porous dielectric material. The pores can be filled with the deposited flowable dielectric material without depositing a continuous film on any exposed metal surface.
    Type: Application
    Filed: August 20, 2014
    Publication date: February 25, 2016
    Inventors: Nerissa Sue Draeger, Kaihan Abidi Ashtiani, Deenesh Padhi, Derek B. Wong, Bart J. van Schravendijk, George Andrew Antonelli, Artur Kolics, Lie Zhao, Patrick A. van Cleemput
  • Patent number: 9245739
    Abstract: Methods for depositing flowable dielectric films using halogen-free precursors and catalysts on a substrate are provided herein. Halogen-free precursors and catalysts include self-catalyzing aminosilane compounds and halogen-free organic acids. Flowable films may be used to fill pores in existing dielectric films on substrates having exposed metallization layers. The methods involve hydrolysis and condensation reactions.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: January 26, 2016
    Assignee: Lam Research Corporation
    Inventors: Nicholas Muga Ndiege, Krishna Nittala, Derek B. Wong, George Andrew Antonelli, Nerissa Sue Draeger, Patrick A. Van Cleemput
  • Publication number: 20150004806
    Abstract: Methods for depositing flowable dielectric films using halogen-free precursors and catalysts on a substrate are provided herein. Halogen-free precursors and catalysts include self-catalyzing aminosilane compounds and halogen-free organic acids. Flowable films may be used to fill pores in existing dielectric films on substrates having exposed metallization layers. The methods involve hydrolysis and condensation reactions.
    Type: Application
    Filed: August 20, 2014
    Publication date: January 1, 2015
    Inventors: Nicholas Muga Ndiege, Krishna Nittala, Derek B. Wong, George Andrew Antonelli, Nerissa Sue Draeger, Patrick A. Van Cleemput
  • Publication number: 20100173074
    Abstract: A method of depositing material on a substrate comprises providing a reactor with a reaction chamber having a first volume, and contacting a surface of a substrate in the reaction chamber with a first precursor at the first chamber volume to react with and deposit a first layer on the substrate. The method further includes enlarging the reaction chamber to a second, larger volume and removing undeposited first precursor and any excess reaction product to end reaction of the first precursor with the substrate.
    Type: Application
    Filed: February 9, 2010
    Publication date: July 8, 2010
    Applicant: NOVELLUS SYSTEMS INC.
    Inventors: Francisco Juarez, Dennis Hausmann, Bunsen Nie, Teresa Pong, Adrianne Tipton, Patrick Van Cleemput
  • Patent number: 7700155
    Abstract: A method of depositing material on a substrate comprises providing a reactor with a reaction chamber having a first volume, and contacting a surface of a substrate in the reaction chamber with a first precursor at the first chamber volume to react with and deposit a first layer on the substrate. The method further includes enlarging the reaction chamber to a second, larger volume and removing undeposited first precursor and any excess reaction product to end reaction of the first precursor with the substrate.
    Type: Grant
    Filed: April 8, 2004
    Date of Patent: April 20, 2010
    Assignee: Novellus Systems, Inc.
    Inventors: Francisco Juarez, Dennis Hausmann, Bunsen Nie, Teresa Pong, Adrianne Tipton, Patrick Van Cleemput
  • Patent number: 7208389
    Abstract: Methods of preparing a porous low-k dielectric material on a substrate are provided. The methods involve the use of ultraviolet radiation to react with and remove porogen from a porogen containing precursor film, leaving a porous low-k dielectric matrix. Methods using oxidative conditions and non-oxidative conditions are described. The methods described may be used to remove porogen from porogen-containing precursor films. The porogen may be a hydrocarbon such as a terpene (e.g., alpha-terpinene) or a norbornene (e.g., ENB). The resulting porous low-k dielectric matrix can then be annealed to remove water and remaining silanols capped to protect it from degradation by ambient conditions, which methods will also be described.
    Type: Grant
    Filed: September 26, 2003
    Date of Patent: April 24, 2007
    Assignee: Novellus Systems, Inc.
    Inventors: Adrianne K. Tipton, Brian G. Lu, Patrick A. Van Cleemput, Michelle T. Schulberg, Qingguo Wu, Haiying Fu, Feng Wang
  • Patent number: 7176144
    Abstract: Methods of preparing a low-k dielectric material on a substrate are provided. The methods involve using plasma techniques to remove porogen from a precursor layer comprising porogen and a dielectric matrix and to protect the dielectric matrix with a silanol capping agent, resulting in a low-k dielectric matrix. Porogen removal and silanol capping can occur concurrently or sequentially. If performed sequentially, silanol capping is performed without first exposing the dielectric matrix to moisture or ambient conditions.
    Type: Grant
    Filed: February 23, 2004
    Date of Patent: February 13, 2007
    Assignee: Novellus Systems, Inc.
    Inventors: Feng Wang, Michelle T. Schulberg, Jianing Sun, Raashina Humayun, Patrick A. Van Cleemput
  • Patent number: 6951765
    Abstract: The present invention pertains to apparatus and methods for introduction of solid precursors and reactants into a supercritical fluid reactor. Solids are dissolved in supercritical fluid solvents in generator apparatus separate from the supercritical fluid reactor. Such apparatus preferably generate saturated solutions of solid precursors via recirculation of supercritical fluids through a vessel containing the solid precursors. Supercritical solutions of the solids are introduced into the reactor, which itself is charged with a supercritical fluid. Supercritical conditions are maintained during the delivery of the dissolved precursor to the reactor. Recirculation of supercritical precursor solutions through the reactor may or may not be implemented in methods of the invention. Methods of the invention are particularly well suited for integrated circuit fabrication, where films are deposited on wafers under supercritical conditions.
    Type: Grant
    Filed: December 12, 2001
    Date of Patent: October 4, 2005
    Assignee: Novellus Systems, Inc.
    Inventors: Sanjay Gopinath, Patrick A. Van Cleemput, Michelle Schulberg, Sasangan Ramanathan, Francisco Juarez, Patrick Joyce