Patents by Inventor Patrick Vannier

Patrick Vannier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9165883
    Abstract: The disclosure relates to a method of fabricating an interconnection structure of an integrated circuit, comprising the steps of: forming a first conductive element within a first dielectric layer; depositing a first etch stop layer above the first conductive element and the first dielectric layer; forming an opening in the first etch stop layer above the first conductive element, to form a first connection area; depositing a second dielectric layer above the etch stop layer and above the first conductive element in the connection area; etching the second dielectric layer to form at least one hole which is at least partially aligned with the connection area; and filling the hole with a conductive material to form a second conductive element in electrical contact with the first conductive element.
    Type: Grant
    Filed: April 21, 2014
    Date of Patent: October 20, 2015
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Patrick Vannier
  • Publication number: 20140225278
    Abstract: The disclosure relates to a method of fabricating an interconnection structure of an integrated circuit, comprising the steps of: forming a first conductive element within a first dielectric layer; depositing a first etch stop layer above the first conductive element and the first dielectric layer; forming an opening in the first etch stop layer above the first conductive element, to form a first connection area; depositing a second dielectric layer above the etch stop layer and above the first conductive element in the connection area; etching the second dielectric layer to form at least one hole which is at least partially aligned with the connection area; and filling the hole with a conductive material to form a second conductive element in electrical contact with the first conductive element.
    Type: Application
    Filed: April 21, 2014
    Publication date: August 14, 2014
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Patrick Vannier
  • Patent number: 8765604
    Abstract: The disclosure relates to a method of fabricating an interconnection structure of an integrated circuit, comprising the steps of: forming a first conductive element within a first dielectric layer; depositing a first etch stop layer above the first conductive element and the first dielectric layer; forming an opening in the first etch stop layer above the first conductive element, to form a first connection area; depositing a second dielectric layer above the etch stop layer and above the first conductive element in the connection area; etching the second dielectric layer to form at least one hole which is at least partially aligned with the connection area; and filling the hole with a conductive material to form a second conductive element in electrical contact with the first conductive element.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: July 1, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Patrick Vannier
  • Patent number: 8492264
    Abstract: A method for forming interconnection levels of an integrated circuit, including the steps of: (a) forming an interconnection level comprising conductive tracks and vias separated by a porous dielectric material; (b) forming, on the interconnection level, a layer of a non-porous insulating material, said layer comprising openings above portions of porous dielectric material; (c) repeating steps (a) and (b) to obtain the adequate number of interconnection levels; and (d) annealing the structure.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: July 23, 2013
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Patrick Vannier
  • Patent number: 8461046
    Abstract: A process for producing an upper metallization level and a via level connecting this upper metallization level to a lower metallization level includes: producing an insulating region on the lower metallization level; producing a hard mask on the insulating region (4, 5) defining the position of the via and metallic line of the upper metallization level; etching the insulating region through the hard mask so as to form a cavity; cleaning the cavity (which forms an undercut at the interface between the hard mask and the insulating region); and completely filling the cavity. The step of completely filling includes at least partially filling the cavity with copper and plugging the undercut. The undercut is plugged by sputtering a plugging material and forming an overlying doped copper layer.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: June 11, 2013
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Patrick Vannier
  • Publication number: 20120153490
    Abstract: The disclosure relates to a method of fabricating an interconnection structure of an integrated circuit, comprising the steps of: forming a first conductive element within a first dielectric layer; depositing a first etch stop layer above the first conductive element and the first dielectric layer; forming an opening in the first etch stop layer above the first conductive element, to form a first connection area; depositing a second dielectric layer above the etch stop layer and above the first conductive element in the connection area; etching the second dielectric layer to form at least one hole which is at least partially aligned with the connection area; and filling the hole with a conductive material to form a second conductive element in electrical contact with the first conductive element.
    Type: Application
    Filed: December 15, 2011
    Publication date: June 21, 2012
    Applicant: STMICROELECTRONICS (CROLLES 2) SAS
    Inventor: Patrick Vannier
  • Publication number: 20120040525
    Abstract: A method for forming interconnection levels of an integrated circuit, including the steps of: (a) forming an interconnection level including conductive tracks and vias separated by a porous dielectric material; (b) forming, on the interconnection level, a layer of a non-porous insulating material, said layer comprising openings above portions of porous dielectric material; (c) repeating steps (a) and (b) to obtain the adequate number of interconnection levels; and (d) annealing the structure.
    Type: Application
    Filed: August 1, 2011
    Publication date: February 16, 2012
    Applicant: STMicroelectronics Crolles 2 SAS
    Inventor: Patrick Vannier
  • Publication number: 20120018889
    Abstract: A process for producing an upper metallization level and a via level connecting this upper metallization level to a lower metallization level includes: producing an insulating region on the lower metallization level; producing a hard mask on the insulating region (4, 5) defining the position of the via and metallic line of the upper metallization level; etching the insulating region through the hard mask so as to form a cavity; cleaning the cavity (which forms an undercut at the interface between the hard mask and the insulating region); and completely filling the cavity. The step of completely filling includes at least partially filling the cavity with copper and plugging the undercut. The undercut is plugged by sputtering a plugging material and forming an overlying doped copper layer.
    Type: Application
    Filed: July 20, 2011
    Publication date: January 26, 2012
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Patrick Vannier
  • Publication number: 20090243101
    Abstract: A method for forming interconnection levels of an integrated circuit, including the steps of: (a) forming an interconnection level comprising conductive tracks and vias separated by a porous dielectric material; (b) forming, on the interconnection level, a layer of a non-porous insulating material, said layer comprising openings above portions of porous dielectric material; (c) repeating steps (a) and (b) to obtain the adequate number of interconnection levels; and (d) annealing the structure.
    Type: Application
    Filed: March 26, 2009
    Publication date: October 1, 2009
    Applicant: STMicroelectronics Crolles 2 SAS
    Inventor: Patrick Vannier