Abstract: A system receives a logic design of a circuit of an integrated circuit and apply a reduced synthesis process to the logical design of the integrated circuit. The reduced synthesis process is less computation intensive compared to the optimized digital implementation synthesis process and generates a netlist having suboptimal delay. The system provides the generated netlist as input to a timing analysis that alters the standard delay computation (through scaling and other means) to predict the timing of a fully optimized netlist. The reduced synthesis process has faster execution time compared to the optimized digital implementation synthesis process but results in comparable performance, power and area that is within a threshold of the results generated using optimized digital implementation synthesis process.

Abstract: A logic network for an integrated circuit is synthesized as follows. The logic network is mapped to a network of lookup tables (LUTs). The LUT mapping is based at least in part on estimated areas of the LUTs. The individual LUTs in the network are improved (LUT optimization), for example using various Boolean optimization techniques. The network of improved LUTs is then reduced to a gate-level netlist of standard cells.

Abstract: A system receives a logic design of a circuit of an integrated circuit and apply a reduced synthesis process to the logical design of the integrated circuit. The reduced synthesis process is less computation intensive compared to the optimized digital implementation synthesis process and generates a netlist having suboptimal delay. The system provides the generated netlist as input to a timing analysis that alters the standard delay computation (through scaling and other means) to predict the timing of a fully optimized netlist. The reduced synthesis process has faster execution time compared to the optimized digital implementation synthesis process but results in comparable performance, power and area that is within a threshold of the results generated using optimized digital implementation synthesis process.

Abstract: A system and method for SAT-sweeping is disclosed. According to one embodiment, a method includes determining gate classes by inputting simulation patterns to gates in an integrated circuit design, selecting a candidate gate based on an inverse topological ordering of the gates, and then selecting a driver gate belonging to the same gate class as the candidate gate. A SAT-solver is called based on the candidate gate and the driver gate to confirm equivalence. The candidate gate and the driver gate are then merged in the integrated circuit design.

Abstract: Techniques and systems for optimizing a logic network are described. Some embodiments automatically identify scenarios where Boolean methods are best driven by truth tables, binary decision diagrams (BDDs) or satisfiability (SAT). Some embodiments use circuit partitioning techniques that are based on hash-tables and topological sorting, and that are capable of grouping nodes with high simplification likelihood and still are able to efficiently scale to large circuits. Some embodiments feature a generalized resubstitution framework based on computing, and implementing, the Boolean difference between two nodes. Some embodiments include enhancements to (i) gradient-based and-inverter-graph (AIG) optimization, (ii) heterogeneous elimination for kerneling, and (iii) revisitation of maximum set of permissible functions (MSPF) computation with BDDs.

Abstract: A system and method for SAT-sweeping is disclosed. According to one embodiment, a method includes determining gate classes by inputting simulation patterns to gates in an integrated circuit design, selecting a candidate gate based on an inverse topological ordering of the gates, and then selecting a driver gate belonging to the same gate class as the candidate gate. A SAT-solver is called based on the candidate gate and the driver gate to confirm equivalence. The candidate gate and the driver gate are then merged in the integrated circuit design.

Abstract: Robust logic optimization on an IC design based on exclusive sum-of-products (ESOP) refactoring is described. ESOP expressions are two-level logic representation forms, similar to sum-of-product SOP representations. However, since ESOPs use exclusive-OR (XOR) instead of OR operators they can be exponentially more compact than sum-of-product (SOP) expressions for important classes of functions. In XOR heavy logic, ESOP expressions allow us to find optimizations that SOPs simply do not have access to.

Abstract: Systems and techniques are described for circuit optimization using Boolean resynthesis. Features described in this disclosure include (i) a theory of Boolean filtering, to drastically reduce the number of gates processed and still retain all possible optimization opportunities, (ii) a weaker notion of maximum set of permissible functions, which can be computed efficiently via truth tables, (iii) a parallel package for truth table computation tailored to speedup Boolean methods, (iv) a generalized refactoring engine which supports multiple representation forms and (v) a Boolean resynthesis flow, which combines these techniques.

Abstract: Techniques and systems for optimizing a logic network are described. Some embodiments automatically identify scenarios where Boolean methods are best driven by truth tables, binary decision diagrams (BDDs) or satisfiability (SAT). Some embodiments use circuit partitioning techniques that are based on hash-tables and topological sorting, and that are capable of grouping nodes with high simplification likelihood and still are able to efficiently scale to large circuits. Some embodiments feature a generalized resubstitution framework based on computing, and implementing, the Boolean difference between two nodes. Some embodiments include enhancements to (i) gradient-based and-inverter-graph (AIG) optimization, (ii) heterogeneous elimination for kerneling, and (iii) revisitation of maximum set of permissible functions (MSPF) computation with BDDs.

Abstract: Systems and techniques for optimizing an integrated circuit (IC) design are described. A logic-function identifier can be determined based on a fan-in combinational-logic-cone, wherein the logic-function identifier corresponds to a logic function that is implemented by the fan-in combinational-logic-cone. An arrival-time-pattern identifier can be determined based on a set of arrival times at inputs of the fan-in combinational-logic-cone. An optimized combinational-logic-cone can be obtained by performing, in addition to optionally other operations, a database lookup by using the logic-function identifier and the arrival-time-pattern identifier. Next, the fan-in combinational-logic-cone can be replaced with the optimized combinational-logic-cone in the IC design.

Abstract: Systems and techniques for optimizing an integrated circuit (IC) design are described. A logic-function identifier can be determined based on a fan-in combinational-logic-cone, wherein the logic-function identifier corresponds to a logic function that is implemented by the fan-in combinational-logic-cone. An arrival-time-pattern identifier can be determined based on a set of arrival times at inputs of the fan-in combinational-logic-cone. An optimized combinational-logic-cone can be obtained by performing, in addition to optionally other operations, a database lookup by using the logic-function identifier and the arrival-time-pattern identifier. Next, the fan-in combinational-logic-cone can be replaced with the optimized combinational-logic-cone in the IC design.

Abstract: Systems and techniques for optimizing timing of an integrated circuit (IC) design are described. A logic-function identifier can be determined based on a fan-in combinational-logic-cone, wherein the logic-function identifier corresponds to a logic function that is implemented by the fan-in combinational-logic-cone. An arrival-time-pattern identifier can be determined based on a set of arrival times at inputs of the fan-in combinational-logic-cone. A database lookup can be performed based on the logic-function identifier and the arrival-time-pattern identifier to obtain an optimized combinational-logic-cone. Next, the fan-in combinational-logic-cone can be replaced with the optimized combinational-logic-cone in the IC design.

Abstract: Systems and techniques for optimizing timing of an integrated circuit (IC) design are described. A logic-function identifier can be determined based on a fan-in combinational-logic-cone, wherein the logic-function identifier corresponds to a logic function that is implemented by the fan-in combinational-logic-cone. An arrival-time-pattern identifier can be determined based on a set of arrival times at inputs of the fan-in combinational-logic-cone. A database lookup can be performed based on the logic-function identifier and the arrival-time-pattern identifier to obtain an optimized combinational-logic-cone. Next, the fan-in combinational-logic-cone can be replaced with the optimized combinational-logic-cone in the IC design.

Abstract: Aspect of the technology are a method of designing a circuit layout and corresponding computer systems and nontransitory computer media. The circuit layout is for use in forming a lithographic mask set for use in fabricating an integrated circuit. In the method the computer system divides a synthesized circuit design into cell partitions along critical paths of the synthesized circuit design. The computer system associates pins of the plurality of cell partitions with normalized pin timing values. The normalized pin timing values store magnitude differences between a reference timing slack and timing slacks of the plurality of pins.

Abstract: Aspect of the technology are a method of designing a circuit layout and corresponding computer systems and nontransitory computer media. The circuit layout is for use in forming a lithographic mask set for use in fabricating an integrated circuit. In the method the computer system divides a synthesized circuit design into cell partitions along critical paths of the synthesized circuit design. The computer system associates pins of the plurality of cell partitions with normalized pin timing values. The normalized pin timing values store magnitude differences between a reference timing slack and timing slacks of the plurality of pins.