Abstract: A router for interconnecting external devices coupled to the router. The router comprises: 1) a switch fabric; and 2) a plurality of routing nodes coupled to the switch fabric, wherein each of the plurality of routing nodes comprises packet processing circuitry for transmitting data packets to, and receiving data packets from, the external devices and for transmitting data packets to, and receiving data packets from, other ones of the plurality of routing nodes via the switch fabric. The packet processing circuitry comprises: i) a first network processor comprising a first plurality of microengines, each of the first plurality of microengines capable of performing security and classification functions associated with the data packets; and ii) a second network processor comprising a second plurality of microengines, each of the second plurality of microengines capable of performing security and classification functions associated with the data packets.

Abstract: A router for interconnecting external devices comprising: 1) a switch fabric; and 2) R routing nodes coupled to the switch fabric. Each of the R routing nodes exchanges data packets with the external devices via network interface ports and with other routing nodes via the switch fabric. A first routing node comprises: i) an inbound network processor for receiving incoming data packets from a network interface port; ii) an outbound network processor for transmitting data packets to the network interface port; and iii) a shared memory accessible by the inbound and outbound network processors for storing a current trie tree search table and a current vector table used to index into the trie tree search table. A control plane processor generates an updated vector table to replace the current vector table and notifies the inbound and outbound network processors that the updated vector table is available.

Abstract: A routing table search circuit for determining a first destination address for a first received data packet. The routing table search circuit comprises: i) a forwarding table containing destination addresses; and ii) a trie tree search table for translating an address portion of the first received data packet into a destination pointer for accessing the first destination address in the forwarding table. A first stage of the trie tree search table is searched using a received address pointer from a previous stage of the trie tree search table and a first m-bit symbol of the address portion. The routing table search circuit also comprises at least one consecutive symbols table and a control circuit for determining that a second consecutive m-bit symbol is the same as the first m-bit symbol. The control circuit then determines a total number of consecutive identical m-bit symbols beginning with the first m-bit symbol.

Abstract: A router comprising a switch fabric and routing nodes coupled to the switch fabric. Each routing node comprises a trie tree search table for storing routing information associated with received variable length subnet masks. The trie tree search table comprises a plurality of stages that are searched by N-bit address symbols derived from the received variable length subnet masks. Each routing node also comprises a control processor for generating the stages associated with the trie tree search table. The control processor generates for each entry in a first one of the plurality of stages: 1) an end flag indicating whether each entry is a leaf or a branch; 2) a subnet flag indicating whether a subnet mask ends at each entry; and 3) a masked flag indicating whether a subnet mask ending at each entry ends on a boundary of an N-bit address symbol associated with entry.

Abstract: A router for interconnecting external devices coupled to the router. The router comprises a switch fabric and a plurality of routing nodes coupled to the switch fabric. Each routing node comprises packet processing circuitry for transmitting data packets to, and receiving data packets from, the external devices and transmitting data packets to, and receiving data packets from, other routing nodes via the switch fabric. The packet processing circuitry comprises a first network processor comprising: i) N microengines for forwarding the data packets, each of the microengines capable of executing a plurality of threads that perform forwarding table lookup operations; and ii) workload distribution circuitry for distributing data packets to the N microengines for forwarding.

Abstract: A router for interconnecting external devices. The router comprises a switch fabric and a plurality of routing nodes coupled to the switch fabric. Each routing node comprises packet processing circuitry for transmitting data packets to, and receiving data packets from, the external devices and for transmitting data packets to, and receiving data packets from, other routing nodes via the switch fabric and control data processing circuitry capable of performing control and management functions. The control data processing circuitry comprises a first network processor for performing control and management functions associated with the router and a second network processor for performing control and management functions associated with the router. The control and management functions are dynamically allocated between the first network processor and the second network processor.

Abstract: A routing table search circuit comprising a forwarding table containing forwarding table entries, each forwarding table entry comprising a destination address, and a content addressable memory (CAM) comprising a CAM lookup table, the CAM receiving a search key and outputting a CAM search result corresponding to the search key from the CAM lookup table. The search key comprises at least: i) a packet type field associated with the first received address and ii) an address field containing a most significant bits portion of the first received address. The routing table search circuit also comprises M pipelined memory stages for storing a trie table that translates the first received address into the first destination address. The M pipelined memory stages are searched using the CAM search result and a remaining bits portion of the first received address. Each of the M pipelined memory stages outputs a stage search result.

Abstract: A router for interconnecting N interfacing peripheral devices. The router comprises a switch fabric and routing nodes coupled to the switch fabric. Each routing node comprises: i) a plurality of physical medium device (PMD) modules for transmitting data packets to and receiving data packets from selected ones of the N interfacing peripheral devices; ii) an input-output processing (IOP) module coupled to the PMD modules and the switch fabric for routing the data packets between the PMD modules and the switch fabric and between the PMD modules; and iii) a classification module associated with the IOP module for classifying a first data packet received from the IOP module. The classification module causes the IOP module to forward the first data packet based on the classification. The router architecture incorporates streams-based billing support, firewall capabilities, and data surveillance functionality.