Abstract: An array of housings with housing bodies and lenses is molded, or an array of housing bodies is molded and bonded with lenses to form an array of housings with housing bodies and lenses. Light-emitting diodes (LEDs) are attached to the housings in the array. An array of metal pads may be bonded to the back of the array or insert molded with the housing array to form bond pads on the back of the housings. The array is singulated to form individual LED modules.

Abstract: A pointer arm for a gauge of a motor vehicle is provided. The pointer arm includes first and second light reflecting surfaces and an an arm portion extending from the first and second light reflecting surfaces. The pointer arm may be supported for rotation about an axis of rotation relative to a scale, and a shroud may be used to support the pointer arm. A cap may be supported on the pointer arm. The cap may include a pin extending into an opening within the pointer arm. The light reflecting surfaces are configured to propagate light around the opening and through the pointer arm.

Abstract: A method is performed in a requester device that is coupled with a responder device by a serial interface. The method is one of selecting an approach to handle an error in a request-response communication between the requester and responder devices over the serial interface. The method includes transmitting a request packet, of the request-response communication, over the serial interface, based on a request from an application that is executing on a logical processor. The method includes reporting the error in the request-response communication to an application-layer module. The method includes selecting an error handling approach, of a plurality of error handling approaches, which is to be used to handle the error, with the application-layer module.

Abstract: Embodiments of the invention include a method for avoiding memory bandwidth utilization during packet processing. The packet processing core receives a plurality of packets. The packet processing core identifies the packet's quality of service (QoS) descriptor. The packet processing core determines that at least one packet should be moved to an off-chip packet stored prior to the packet being transmitted to the egress port. The packet processing core bases that determination, at least in part, on the packet's QoS descriptor. The packet processing core moves the determined packets to the off-chip packet store. The packet processing core determines that at least one packet should not be moved to the off-chip packet store prior to the packet being transmitted to the egress port. This determination is also made, at least in part, based on the packet's QoS descriptor.

Abstract: A safety catch mechanism, comprising a safety catch that is captively attached to the barrel of a nail gun by matching tracks on both said safety catch and said barrel, facing each other, so that said safety catch is allowed to move only in the forward and backward directions along the barrel of the nail gun in the direction of the motion of the nails, is disclosed. A forward pushing means keeps the forward end of the safety catch beyond the muzzle of the nail gun in the initial secured position. As the safety catch is pushed back, the trigger of the nail gun is activated.

Abstract: Embodiments of the invention include a method for avoiding memory bandwidth utilization during packet processing. The packet processing core receives a plurality of packets. The packet processing core identifies the packet's quality of service (QoS) descriptor. The packet processing core determines that at least one packet should be moved to an off-chip packet stored prior to the packet being transmitted to the egress port. The packet processing core bases that determination, at least in part, on the packet's QoS descriptor. The packet processing core moves the determined packets to the off-chip packet store. The packet processing core determines that at least one packet should not be moved to the off-chip packet store prior to the packet being transmitted to the egress port. This determination is also made, at least in part, based on the packet's QoS descriptor.

Abstract: A hierarchical pipelined distributed scheduling traffic manager includes multiple hierarchical levels to perform hierarchical winner selection and propagation in a pipeline including selecting and propagating winner queues of a lower level to subsequent levels to determine one final winning queue. The winner selection and propagation is performed in parallel between the levels to reduce the time required in selecting the final winning queue. In some embodiments, the hierarchical traffic manager is separated into multiple separate sliced hierarchical traffic managers to distributively process the traffic.

Abstract: An array of housings with housing bodies and lenses is molded, or an array of housing bodies is molded and bonded with lenses to form an array of housings with housing bodies and lenses. Light-emitting diodes (LEDs) are attached to the housings in the array. An array of metal pads may be bonded to the back of the array or insert molded with the housing array to form bond pads on the back of the housings. The array is singulated to form individual LED modules.

Abstract: A light emitter includes a light-emitting device (LED) die and an optical element over the LED die. The optical element includes a lens, a window element, and a bond at an interface disposed between the lens and the window element. The window element may be a wavelength converting element or an optically flat plate. The window element may be directly bonded or fused to the lens, or the window element may be bonded by one or more intermediate bonding layers to the lens. The bond between the window element and the lens may have a refractive index similar to that of the window element, the lens, or both.

Abstract: A hierarchical pipelined distributed scheduling traffic manager includes multiple hierarchical levels to perform hierarchical winner selection and propagation in a pipeline including selecting and propagating winner queues of a lower level to subsequent levels to determine one final winning queue. The winner selection and propagation is performed in parallel between the levels to reduce the time required in selecting the final winning queue. In some embodiments, the hierarchical traffic manager is separated into multiple separate sliced hierarchical traffic managers to distributively process the traffic.

Abstract: A reconfigurable liquid crystal based optical add/drop multiplexer system and method are provided which incorporates switching, variable attenuation, and multiplexing/demultiplexing capabilities. In a preferred embodiment, an array of optical rails is provided such that the integration of multiplexing/demultiplexing, switching, and variable optical attenuation functionalities are achieved. The module is also able to perform add and drop functions independently. The system has no moving parts so that the module is durable and very reliable. The system may include a feedback system for performing channel equalization.

Abstract: The specification describes optical fiber coating materials and methods for making optical fiber gratings wherein the material of the optical fiber coatings comprises vinyl ether functionalized monomers, together with oligomeric or polymeric thickeners and a cationic photoinitiator. These coating materials are highly transparent to UV radiation used to write optical gratings in the optical fibers but still absorb sufficiently at other wavelengths to be cured effectively using UV radiation.

Abstract: The specification describes processes for synthesizing vinyl ether functionalized oligomers or polymers, and methods for coating optical fibers with formulations containing these oligomers or polymers. Optical fibers coated with these formulations can be highly transparent to radiation used to write optical gratings in the optical fibers.

Abstract: A flash memory cell structure comprising a semiconductor substrate having a first transistor and a second transistor formed thereon. The first transistor has a stacked gate and a first source/drain regions, wherein the stacked gate further includes a floating gate and a control gate. The control gate is formed above the floating gate. The second transistor is electrically connected in series with the first transistor. The second transistor functions as a select transistor and includes a gate and a second source/drain regions.

Abstract: A method for detecting a half-full condition of a first-in, first-out memory array. The method of the invention includes the steps of a) moving a write pointer through the array to write data to alternating rows of the memory array; b) moving a read pointer through the array to read data from the alternating rows of the memory array in first-in, first-out order; and c) providing a half-full indication when the read pointer and the write pointer point to adjacent rows in the memory array. This method eliminates the need to route lines across the array to detect a half-full condition, thereby reducing die and power requirements and offering an increase in speed.

Abstract: A d.c. electric motor has a permanent magnet stator and a wound rotor both mounted within a body. An end cover is fixed to the body and carries a thermal switch which is disposed inside the body adjacent to the windings and controls the supply current to the motor.