Patents by Inventor Patrick Yue

Patrick Yue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220125894
    Abstract: The present disclosure relates to compositions and methods useful for assessing the efficacy in a patient having suffered from intracranial hemorrhage while undergoing an anticoagulation treatment with a factor Xa (fXa) inhibitor. The method can include administering to the patient a fXa derivative that has reduced catalytic activity as compared to the wild-type fXa protein, is capable of binding to the factor Xa inhibitor and cannot assemble into a prothrombinase complex; obtaining a blood sample from the patient following the administration; and measuring an anti-fXa activity in the sample, wherein the anti-fXa activity reflects the hemostatic efficacy in the patient. Once the assessment is made, suitable medical interventions can be implemented.
    Type: Application
    Filed: February 7, 2020
    Publication date: April 28, 2022
    Applicant: Alexion Pharmaceuticals, Inc.
    Inventor: Patrick Yue
  • Patent number: 6850117
    Abstract: The present invention provides a breakdown resistant transistor structure for amplifying communication signals. This structure includes a first NMOS transistor having a source connected to ground and a first gate for receiving the input radio frequency signal. The first gate is disposed above a first insulator and the first NMOS transistor having a first transconductance and a first breakdown voltage associated therewith. Also included is a second NMOS transistor having a source connected to the drain of the first NMOS transistor, a gate connected to the reference DC voltage, and a drain that provides the output for the amplified radio signal, the load being disposed between the reference DC voltage and the drain of the second NMOS transistor. The second gate is disposed above a second insulator, the second NMOS transistor has a second transconductance and a second breakdown voltage associated therewith, and the second insulator may be thicker than the first insulator.
    Type: Grant
    Filed: January 7, 2003
    Date of Patent: February 1, 2005
    Assignee: Atheros Communications, Inc.
    Inventors: David J. Weber, Patrick Yue, David Su
  • Publication number: 20030155976
    Abstract: The present invention provides a breakdown resistant transistor structure for amplifying communication signals. This structure includes a first NMOS transistor having a source connected to ground and a first gate for receiving the input radio frequency signal. The first gate is disposed above a first insulator and the first NMOS transistor having a first transconductance and a first breakdown voltage associated therewith. Also included is a second NMOS transistor having a source connected to the drain of the first NMOS transistor, a gate connected to the reference DC voltage, and a drain that provides the output for the amplified radio signal, the load being disposed between the reference DC voltage and the drain of the second NMOS transistor. The second gate is disposed above a second insulator, the second NMOS transistor has a second transconductance and a second breakdown voltage associated therewith, and the second insulator may be thicker than the first insulator.
    Type: Application
    Filed: January 7, 2003
    Publication date: August 21, 2003
    Inventors: David J. Weber, Patrick Yue, David Su
  • Patent number: 6504433
    Abstract: The present invention provides a breakdown resistant transistor structure for amplifying communication signals. This structure includes a first NMOS transistor having a source connected to ground and a first gate for receiving the input radio frequency signal. The first gate is disposed above a first insulator and the first NMOS transistor having a first transconductance and a first breakdown voltage associated therewith. Also included is a second NMOS transistor having a source connected to the drain of the first NMOS transistor, a gate connected to the reference DC voltage, and a drain that provides the output for the amplified radio signal, the load being disposed between the reference DC voltage and the drain of the second NMOS transistor. The second gate is disposed above a second insulator, the second NMOS transistor has a second transconductance and a second breakdown voltage associated therewith, and the second insulator may be thicker than the first insulator.
    Type: Grant
    Filed: September 15, 2000
    Date of Patent: January 7, 2003
    Assignee: Atheros Communications, Inc.
    Inventors: David J. Weber, Patrick Yue, David Su
  • Patent number: 6504431
    Abstract: The present invention provides a breakdown resistant transistor structure for amplifying communication signals. This structure includes a first NMOS transistor having a source connected to ground and a first gate for receiving the input radio frequency signal. The first gate is disposed above a first insulator and the first NMOS transistor having a first transconductance and a first breakdown voltage associated therewith. Also included is a second NMOS transistor having a source connected to the drain of the first NMOS transistor, a gate connected to the reference DC voltage, and a drain that provides the output for the amplified radio signal, the load being disposed between the reference DC voltage and the drain of the second NMOS transistor. The second gate is disposed above a second insulator, the second NMOS transistor has a second transconductance and a second breakdown voltage associated therewith, and the second insulator may be thicker than the first insulator.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: January 7, 2003
    Assignee: Atheros Communications, Inc.
    Inventors: David J. Weber, Patrick Yue, David Su
  • Publication number: 20020105380
    Abstract: The present invention provides a breakdown resistant transistor structure for amplifying communication signals. This structure includes a first NMOS transistor having a source connected to ground and a first gate for receiving the input radio frequency signal. The first gate is disposed above a first insulator and the first NMOS transistor having a first transconductance and a first breakdown voltage associated therewith. Also included is a second NMOS transistor having a source connected to the drain of the first NMOS transistor, a gate connected to the reference DC voltage, and a drain that provides the output for the amplified radio signal, the load being disposed between the reference DC voltage and the drain of the second NMOS transistor. The second gate is disposed above a second insulator, the second NMOS transistor has a second transconductance and a second breakdown voltage associated therewith, and the second insulator may be thicker than the first insulator.
    Type: Application
    Filed: March 26, 2002
    Publication date: August 8, 2002
    Applicant: ATHEROS COMMUNICATIONS, INC.
    Inventors: David J. Weber, Patrick Yue, David Su