Patents by Inventor Patrik Algotsson

Patrik Algotsson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100055860
    Abstract: In the fabrication of an integrated circuit, a shallow trench for isolation of a vertical bipolar transistor comprised in the circuit is fabricated by providing a semiconductor substrate of a first doping type. A buried collector region of a second doping type for the bipolar transistor is formed in the substrate. A silicon layer is epitaxially grown on top of the substrate. An active region of the second doping type for the bipolar transistor is formed in the epitaxially grown silicon layer, the active region being located above the buried collector region. A first trench is formed in the epitaxially grown silicon layer and the silicon substrate, the first trench surrounding, in a horizontal plane, the active region and extending vertically a distance into the substrate. An electrically insulating material is formed in the first trench.
    Type: Application
    Filed: September 17, 2009
    Publication date: March 4, 2010
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Ted Johansson, Hans Norström, Patrik Algotsson
  • Patent number: 7008836
    Abstract: A method to provide a triple well in an epitaxially based CMOS or B:CMOS process comprises the step of implanting the triple well prior to the epitaxial deposition.
    Type: Grant
    Filed: March 26, 2004
    Date of Patent: March 7, 2006
    Assignee: Infineon Technologies Wireless Solutions Sweden AB
    Inventors: Patrik Algotsson, Karin Andersson, Hans Norström
  • Publication number: 20050020003
    Abstract: An IC fabrication method comprises the steps of: providing a substrate (10, 41); forming an active region (41) for a bipolar transistor and an active region (41) for a MOS device in the substrate (10); forming isolation areas (81) around, in a horizontal plane, the active regions; forming a MOS gate region (111, 112) on the active region for the MOS device; forming a layer (141) of an insulating material on the MOS gate region and on the active region (31) for the transistor; and defining a base region in the active region for the transistor by producing an opening (143) in the insulating layer (141) such that the remaining portions of the insulating layer (141) partly cover the active region for the bipolar transistor. The insulating layer (141) remains on the MOS gate region to encapsulate and protect the MOS gate region during subsequent manufacturing steps.
    Type: Application
    Filed: October 31, 2003
    Publication date: January 27, 2005
    Inventors: Ted Johansson, Hans Norstrom, Patrik Algotsson
  • Publication number: 20040219733
    Abstract: A method to provide a triple well in an epitaxially based CMOS or B:CMOS process comprises the step of implanting the triple well prior to the epitaxial deposition.
    Type: Application
    Filed: March 26, 2004
    Publication date: November 4, 2004
    Inventors: Patrik Algotsson, Karin Andersson, Hans Norstrom