Patents by Inventor Patrik Eder
Patrik Eder has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240143423Abstract: Techniques, described herein, include solutions for evaluating a pre-failure condition of a data link. The techniques described allow for detection of the pre-failure condition before actual failure of the data link. A device may receive a first set of training data and compare the first set of training data to a pre-determined set of training data to obtain a first set of values at a first time. The process may be repeated at a second time with a second set of training data and a second set of values respectively. First and second quality metrics may be obtained using the first and second set of values respectively. Based on the first and second quality metrics and a time interval between the first and second times, the pre-failure condition may be determined.Type: ApplicationFiled: November 2, 2022Publication date: May 2, 2024Inventors: Patrik Eder, Christian Mueller
-
Publication number: 20240004992Abstract: In an embodiment an integrated circuit comprises a plurality of ports. Of a plurality of gating circuits, each gating circuit blocks or grants access to at least one of the ports depending on a release signal. From a plurality of configuration registers, each configuration register for stores the information to which group a gating circuit of the plurality of gating circuits belongs. A tag evaluation circuit receives an identifier from an access request from a component and outputs a group identifier for the access. There is a plurality of comparison circuits. Each comparison circuit compares the group identifier with the content of one of the configuration registers and outputs the release signal to a gating circuit of the plurality of gating circuits.Type: ApplicationFiled: June 30, 2023Publication date: January 4, 2024Inventors: Patrik Eder, Rainer Wolfgang Kaiser
-
Publication number: 20230267094Abstract: In various examples, a system on a chip is provided that is configured to be operated in a debug mode. The system on a chip includes a plurality of processor cores including a plurality of virtual machines and a further processor core, configured to, in the debug mode, initially execute first debug instructions after the system on a chip has started operating. The first debug instructions are configured to cause the further processor core to make a debug setting that, after the first debug instructions are executed, prevents a processor core executing second debug instructions from accessing at least one of the virtual machines and allows the processor core executing the second debug instructions to access at least one other of the virtual machines.Type: ApplicationFiled: February 24, 2022Publication date: August 24, 2023Inventors: Albrecht Mayer, Patrik Eder, Kajetan Nuernberger
-
Patent number: 11698412Abstract: Techniques and mechanisms to exchange test, debug or trace (TDT) information via a general purpose input/output (I/O) interface. In an embodiment, an I/O interface of a device is coupled to an external TDT unit, wherein the I/O interface is compatible with an interconnect standard that supports communication of data other than any test information, debug information or trace information. One or more circuit components reside on the device or are otherwise coupled to the external TDT unit via the I/O interface. Information exchanged via the I/O interface is generated by, or results in, the performance of one or more TDT operations to evaluate the one or more circuit components. In another embodiment, the glue logic of the device interfaces the I/O interface with a test access point that is coupled between the one or more circuit components and the I/O interface.Type: GrantFiled: November 30, 2021Date of Patent: July 11, 2023Assignee: Intel CorporationInventors: Rolf H. Kuehnis, Sankaran M. Menon, Patrik Eder
-
Publication number: 20220082617Abstract: Techniques and mechanisms to exchange test, debug or trace (TDT) information via a general purpose input/output (I/O) interface. In an embodiment, an I/O interface of a device is coupled to an external TDT unit, wherein the I/O interface is compatible with an interconnect standard that supports communication of data other than any test information, debug information or trace information. One or more circuit components reside on the device or are otherwise coupled to the external TDT unit via the I/O interface. Information exchanged via the I/O interface is generated by, or results in, the performance of one or more TDT operations to evaluate the one or more circuit components. In another embodiment, the glue logic of the device interfaces the I/O interface with a test access point that is coupled between the one or more circuit components and the I/O interface.Type: ApplicationFiled: November 30, 2021Publication date: March 17, 2022Applicant: Intel CorporationInventors: Rolf H. Kuehnis, Sankaran M. Menon, Patrik Eder
-
Patent number: 11193973Abstract: Techniques and mechanisms to exchange test, debug or trace (TDT) information via a general purpose input/output (I/O) interface. In an embodiment, an I/O interface of a device is coupled to an external TDT unit, wherein the I/O interface is compatible with an interconnect standard that supports communication of data other than any test information, debug information or trace information. One or more circuit components reside on the device or are otherwise coupled to the external TDT unit via the I/O interface. Information exchanged via the I/O interface is generated by, or results in, the performance of one or more TDT operations to evaluate the one or more circuit components. In another embodiment, the glue logic of the device interfaces the I/O interface with a test access point that is coupled between the one or more circuit components and the I/O interface.Type: GrantFiled: July 17, 2020Date of Patent: December 7, 2021Assignee: Intel CorporationInventors: Rolf H. Kuehnis, Sankaran M. Menon, Patrik Eder
-
Publication number: 20210367366Abstract: A circuitry is disclosed having one or more circuits and a connector portion coupled that is to the one or more circuits. The connector portion includes a plurality of pins, at least some of the pins having assigned functionality, and wherein at least one first pin is to activate a mechanism to bring the one or more circuits into an electrically safe state. The circuitry is configured, in case the connector portion is coupled with a first connector in a first orientation, to allow the one or more circuits to operate properly via the connector portion. The circuitry is also configured so that in a case where the connector portion is coupled with a second connector in a second orientation different from the first orientation, the at least one first pin of the plurality of pins receives a reference potential that triggers activation of a safety mechanism.Type: ApplicationFiled: May 25, 2021Publication date: November 25, 2021Inventors: Albrecht Mayer, Patrik Eder
-
Patent number: 11171856Abstract: An apparatus is provided which comprises: a first network interface (NI) to receive data from a source; a second NI coupled to a target; and a circuitry to generate a sequence of source timestamps and a sequence of target timestamps, wherein the first NI is to receive the sequence of source timestamps, and associate a first source timestamp of the sequence of source timestamps with the data, and wherein the second NI is to receive: the data with the first source timestamp from the first NI and the sequence of target timestamps from the circuitry, the second NI to generate a timestamp for the data, based at least in part on the first source timestamp and a first target timestamp of the sequence of target timestamps.Type: GrantFiled: December 7, 2017Date of Patent: November 9, 2021Assignee: INTEL CORPORATIONInventors: Pradeep Kumar, Amit Badole, Arumugam Vijayaraman, Helmut Reinig, Patrik Eder, Vladimir Todorov, Abhiram Anantharamu
-
Patent number: 11138083Abstract: Methods and apparatuses relating to a multiple master capable debug interface are described. In one embodiment, an apparatus includes a device circuit, a wireless connector circuit, and a switching circuit coupled between the device circuit and the wireless connector circuit to switch a debug and test mastership from the wireless connector circuit to a debug and test tool, wirelessly connected to the wireless connector circuit, to perform a debug and test operation on the device circuit.Type: GrantFiled: October 8, 2019Date of Patent: October 5, 2021Assignee: Intel CorporationInventors: Patrik Eder, Rolf H. Kuehnis, Enrico D. Carrieri
-
Publication number: 20200348360Abstract: Techniques and mechanisms to exchange test, debug or trace (TDT) information via a general purpose input/output (I/O) interface. In an embodiment, an I/O interface of a device is coupled to an external TDT unit, wherein the I/O interface is compatible with an interconnect standard that supports communication of data other than any test information, debug information or trace information. One or more circuit components reside on the device or are otherwise coupled to the external TDT unit via the I/O interface. Information exchanged via the I/O interface is generated by, or results in, the performance of one or more TDT operations to evaluate the one or more circuit components. In another embodiment, the glue logic of the device interfaces the I/O interface with a test access point that is coupled between the one or more circuit components and the I/O interface.Type: ApplicationFiled: July 17, 2020Publication date: November 5, 2020Applicant: Intel IP CorporationInventors: Rolf H. Kuehnis, Sankaran M. Menon, Patrik Eder
-
Patent number: 10795399Abstract: One embodiment provides a master device in a bus system. The master device includes bus interface circuitry to exchange commands and data with a slave device in communication with the master device; and test sequence generation logic to generate at least one test sequence, each test sequence having a corresponding unique clock signal having a unique clock frequency; the test sequence generation logic also to transmit the at least one test sequence and the corresponding unique clock signal to the slave device; the test signal generation logic also to determine, based on feedback from the slave device, if the slave device is capable of communicating with the master device using the unique clock frequency.Type: GrantFiled: December 27, 2017Date of Patent: October 6, 2020Assignee: Intel CorporationInventors: Patrik Eder, Rolf Kuehnis, Enrico Carrieri
-
Patent number: 10718812Abstract: Techniques and mechanisms to exchange test, debug or trace (TDT) information via a general purpose input/output (I/O) interface. In an embodiment, an I/O interface of a device is coupled to an external TDT unit, wherein the I/O interface is compatible with an interconnect standard that supports communication of data other than any test information, debug information or trace information. One or more circuit components reside on the device or are otherwise coupled to the external TDT unit via the I/O interface. Information exchanged via the I/O interface is generated by, or results in, the performance of one or more TDT operations to evaluate the one or more circuit components. In another embodiment, the glue logic of the device interfaces the I/O interface with a test access point that is coupled between the one or more circuit components and the I/O interface.Type: GrantFiled: August 20, 2018Date of Patent: July 21, 2020Assignee: Intel IP CorporationInventors: Rolf H. Kuehnis, Sankaran M. Menon, Patrik Eder
-
Publication number: 20200034260Abstract: Methods and apparatuses relating to a multiple master capable debug interface are described. In one embodiment, an apparatus includes a device circuit, a wireless connector circuit, and a switching circuit coupled between the device circuit and the wireless connector circuit to switch a debug and test mastership from the wireless connector circuit to a debug and test tool, wirelessly connected to the wireless connector circuit, to perform a debug and test operation on the device circuit.Type: ApplicationFiled: October 8, 2019Publication date: January 30, 2020Inventors: PATRIK EDER, ROLF H. KUEHNIS, ENRICO D. CARRIERI
-
Patent number: 10481990Abstract: Methods and apparatuses relating to a multiple master capable debug interface are described. In one embodiment, an apparatus includes a device circuit, a debug and test access port to debug and test the device circuit, and a switching circuit to switch a debug and test mastership between the debug and test access port and a data access port to the device circuit that is not dedicated to debug and test.Type: GrantFiled: March 30, 2017Date of Patent: November 19, 2019Assignee: Intel CorporationInventors: Patrik Eder, Rolf H. Kuehnis, Enrico D. Carrieri
-
Publication number: 20190219634Abstract: Techniques and mechanisms to exchange test, debug or trace (TDT) information via a general purpose input/output (I/O) interface. In an embodiment, an I/O interface of a device is coupled to an external TDT unit, wherein the I/O interface is compatible with an interconnect standard that supports communication of data other than any test information, debug information or trace information. One or more circuit components reside on the device or are otherwise coupled to the external TDT unit via the I/O interface. Information exchanged via the I/O interface is generated by, or results in, the performance of one or more TDT operations to evaluate the one or more circuit components. In another embodiment, the glue logic of the device interfaces the I/O interface with a test access point that is coupled between the one or more circuit components and the I/O interface.Type: ApplicationFiled: August 20, 2018Publication date: July 18, 2019Applicant: Intel IP CorporationInventors: Rolf H. KUEHNIS, Sankaran M. MENON, Patrik EDER
-
Publication number: 20190080258Abstract: Embodiments of the present disclosure may relate to an apparatus with an observation hub that includes a machine-learning model, where the observation hub is to determine a state of an apparatus based at least in part on the machine-learning model and trace data received from one or more trace sources, and alter an operating condition of the apparatus based at least in part on the determined state of the apparatus. Embodiments may also include a multi-buffer trace unit to change one or more of a sort rule, a trigger rule, an enforcement rule, or a filter rule of the multi-buffer trace unit based at least in part on the determined state of the apparatus. Other embodiments may be described and/or claimed.Type: ApplicationFiled: September 13, 2017Publication date: March 14, 2019Inventors: Patrik Eder, Christian Horak, Joseph F. Cramer
-
Publication number: 20190033910Abstract: One embodiment provides a master device in a bus system. The master device includes bus interface circuitry to exchange commands and data with a slave device in communication with the master device; and test sequence generation logic to generate at least one test sequence, each test sequence having a corresponding unique clock signal having a unique clock frequency; the test sequence generation logic also to transmit the at least one test sequence and the corresponding unique clock signal to the slave device; the test signal generation logic also to determine, based on feedback from the slave device, if the slave device is capable of communicating with the master device using the unique clock frequency.Type: ApplicationFiled: December 27, 2017Publication date: January 31, 2019Applicant: Intel CorporationInventors: PATRIK EDER, ROLF KUEHNIS, ENRICO CARRIERI
-
Publication number: 20190036803Abstract: An apparatus is provided which comprises: a first network interface (NI) to receive data from a source; a second NI coupled to a target; and a circuitry to generate a sequence of source timestamps and a sequence of target timestamps, wherein the first NI is to receive the sequence of source timestamps, and associate a first source timestamp of the sequence of source timestamps with the data, and wherein the second NI is to receive: the data with the first source timestamp from the first NI and the sequence of target timestamps from the circuitry, the second NI to generate a timestamp for the data, based at least in part on the first source timestamp and a first target timestamp of the sequence of target timestamps.Type: ApplicationFiled: December 7, 2017Publication date: January 31, 2019Applicant: Intel IP CorporationInventors: Pradeep Kumar, Amit Badole, Arumugam Vijayaraman, Helmut Reinig, Patrik Eder, Vladimir Todorov, Abhiram Anantharamu
-
Patent number: 10054636Abstract: Techniques and mechanisms to exchange test, debug or trace (TDT) information via a general purpose input/output (I/O) interface. In an embodiment, an I/O interface of a device is coupled to an external TDT unit, wherein the I/O interface is compatible with an interconnect standard that supports communication of data other than any test information, debug information or trace information. One or more circuit components reside on the device or are otherwise coupled to the external TDT unit via the I/O interface. Information exchanged via the I/O interface is generated by, or results in, the performance of one or more TDT operations to evaluate the one or more circuit components. In another embodiment, the glue logic of the device interfaces the I/O interface with a test access point that is coupled between the one or more circuit components and the I/O interface.Type: GrantFiled: March 30, 2016Date of Patent: August 21, 2018Assignee: Intel IP CorporationInventors: Rolf H. Kuehnis, Sankaran M. Menon, Patrik Eder
-
Publication number: 20180225063Abstract: Techniques and mechanisms to determine a selective buffering of various trace data to different respective buffers. In an embodiment, sort rules indicate trace data attributes that are each to correspond to a different respective buffer. The sort rules are enforced during a runtime session to concurrently sort different items of trace data, based on associated trace data attributes, for storage each to a corresponding buffer. In another embodiment, trigger rules are enforced during the runtime session to selectively debuffer only some trace data based on trigger conditions variously corresponding to different respective trace data types. In still another embodiment, enforcement of sort rules and/or trigger rules is modified during the runtime session to enable dynamic changes to the buffering or debuffering of trace data.Type: ApplicationFiled: February 8, 2017Publication date: August 9, 2018Inventors: Amit Kumar Singhvi, Gerhard Hierl, Patrik Eder, Christian Horak