Abstract: The invention relates to a hybrid network device comprising a server interface enabling access to a server system memory, a network switch comprising a packet processing engine configured to process packets routed through the switch and a switch packet buffer configured to queue packets before transmission, at least one network interface; and at least one a bus mastering DMA controller configured to access the data of said server system memory via said at least one server interface and transfer said data to and from said hybrid network device. According to one aspect of the invention, a bus transfer arbiter configured to control the data transfer from the server memory to the packet processing engine of said hybrid network device.

Abstract: Converters and a corresponding method for converting serial data to parallel format and vice versa, particularly for use in switches for telecommunications applications. The converters comprise a storage element associated with each serial channel and comprising two arrays of storage elements. At any one time, the storage elements are accessed sequentially while those of the other array are accessed in parallel. A data bus, divided into portions by buffers, connects the by buffers, connects the serial channel to all storage cells in an associated storage element. For serial to parallel conversion, the buffers latch data from one bus portion to the next in accordance with a write cycle during which one storage element is written. Writing commences from the bus portion furthest from the incoming serial channel and storage elements on either side of a buffer are written simultaneously. The resulting delay between writing arrays words allows checking of the data such as synchronization.

Abstract: The invention relates to a buffer memory, method and a buffer controller for queue management usable in an ATM switch. An object of the invention is to achieve a high frequency throughput of data cells in the buffer memory. This object is achieved by using a buffer memory which is organized as 256*(424+8) SRAM-cells. The memory is used for holding ten queues, one for each incoming channel and two free-queues containing idle cells.

Abstract: The invention relates to a method and an arrangement for multicasting, i.e. point to multipoint transmission of a data packet. A packet is copied and transmitted to multiple addresses. In the multicasting arrangement, switch core and input and output port are connected to input and output links, respectively, for transmitting data packets. According to the invention, the input port is adapted to detect a multicasting packet received on an input link or from an output port and send the multicasting packet to an output port. The output port is adapted to detect the multicasting packet, copy the data packet, modify an address portion of the multicasting packet, send one packet on the output link and return one packet with the modified address portion to an input port. Preferably, the input port and the output port are integrated in a link interface having a direct channel for returning the data packet.