Abstract: A plasma power limiter fabricated using wafer-level fabrication techniques with other circuit elements. The power limiter includes a signal substrate having a first side and a second side, an input signal line formed on the first side, a signal transmission line formed on the second side and an output signal line formed on the first side. The power limiter also includes a ground substrate having a first side and a second side, and being bonded to the signal substrate to form a sealed cavity including an ionizable gas therebetween. The ground substrate includes a ground metal layer formed on the second side. A signal propagating on the input signal line at a power level greater than a threshold power level generates a voltage potential across the cavity that ionizes the gas and generates a plasma discharge, and limits power of the output signal coupled to the output signal line.

Abstract: A plasma power limiter fabricated using wafer-level fabrication techniques with other circuit elements. The power limiter includes a signal substrate having a first side and a second side, an input signal line formed on the first side, a signal transmission line formed on the second side and an output signal line formed on the first side. The power limiter also includes a ground substrate having a first side and a second side, and being bonded to the signal substrate to form a sealed cavity including an ionizable gas therebetween. The ground substrate includes a ground metal layer formed on the second side. A signal propagating on the input signal line at a power level greater than a threshold power level generates a voltage potential across the cavity that ionizes the gas and generates a plasma discharge, and limits power of the output signal coupled to the output signal line.

Abstract: Monolithic microwave integrated circuit (MMIC) components and micro electromechanical systems (MEMS) components are integrated onto a single substrate at a wafer scale, by first performing MMIC and MEMS fabrication on a front face of a thick substrate wafer, bonding the substrate wafer to a cover wafer, thinning the back face of the substrate wafer and, finally, completing MMIC and MEMS fabrication on the back face of the thinned substrate wafer. The fabrication process is facilitated by use of a guard ring between the wafers to provide additional mechanical support to the substrate wafer and to protect the devices while the MMIC/MEMS fabrication is completed, and by a low temperature bonding process to join the substrate wafer and the cover wafer at multiple device cavity seal rings.