Patents by Inventor Patty Pei-Ling Chang-Chien
Patty Pei-Ling Chang-Chien has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8686813Abstract: An electronic system. The electronic system includes a waveguide structure having a first waveguide-coupling point and a second waveguide-coupling point and an active electronic circuit having a first circuit-coupling point and a second circuit-coupling point. The second waveguide-coupling point is coupled to the first circuit-coupling point; the system is capable of receiving an input signal at the first waveguide-coupling point and transmitting an output signal at the second circuit-coupling point and/or receiving the input signal at the second circuit-coupling point and transmitting the output signal at the first waveguide-coupling point; the input signal and the output signal have frequencies in a terahertz frequency range; and the system is fabricated as a monolithic integrated structure having the waveguide structure fabricated by micromachining and the circuit fabricated monolithically.Type: GrantFiled: August 29, 2009Date of Patent: April 1, 2014Assignee: Northrop Grumman Systems CorporationInventors: William Roland Deal, Kevin Masaru Kung Hoong Leong, Vesna Radisic, Patty Pei-Ling Chang-Chien, Richard Lai
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Patent number: 8598465Abstract: A wafer-scale assembly circuit including a plurality of metal interconnect layers, where each metal layer includes patterned metal portions and where at least some of the patterned metal portions are RF signal lines. The circuit further includes at least one benzocyclobutene layer provided between two metal interconnect layers that includes at least one trench via formed around a perimeter of the benzocyclobutene layer at a circuit sealing ring, where the trench via provides a hermetic seal at the sealing ring. The benzocyclobutene layer also includes a plurality of stabilizing post vias formed through the benzocyclobutene layer adjacent to the trench via proximate to the sealing ring and extending around the perimeter of the benzocyclobutene layer, where the stabilizing vias operate to prevent the benzocyclobutene layer from shrinking in size.Type: GrantFiled: January 27, 2011Date of Patent: December 3, 2013Assignee: Northrop Grumman Systems CorporationInventors: David M. Eaves, Xiang Zeng, Kelly J. Hennig, Patty Pei-Ling Chang-Chien
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Patent number: 7919839Abstract: A semiconductor structure, such as a wafer-level package or a vertically stacked structure. The wafer-level package includes a substrate wafer on which an integrated circuit is formed. A cover wafer is bonded to the substrate wafer to provide a cavity between the substrate wafer and the cover wafer in which the integrated circuit is hermetically sealed. Vias are formed through the substrate wafer and make electrical contact with signal and ground traces formed on the substrate wafer within the cavity, where the traces are electrically coupled to the integrated circuit. Probe pads are formed on the substrate wafer outside of the cavity and are in electrical contact with the vias. A support post is provided directly beneath the probe pad so that when pressure is applied to the probe pad from the probe for testing purposes, the support post prevents the substrate wafer from flexing and being damaged.Type: GrantFiled: July 24, 2007Date of Patent: April 5, 2011Assignee: Northrop Grumman Systems CorporationInventors: Patty Pei-Ling Chang-Chien, Kelly Jill Tornquist Hennig
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Publication number: 20110050371Abstract: An electronic system. The electronic system includes a waveguide structure having a first waveguide-coupling point and a second waveguide-coupling point and an active electronic circuit having a first circuit-coupling point and a second circuit-coupling point. The second waveguide-coupling point is coupled to the first circuit-coupling point; the system is capable of receiving an input signal at the first waveguide-coupling point and transmitting an output signal at the second circuit-coupling point and/or receiving the input signal at the second circuit-coupling point and transmitting the output signal at the first waveguide-coupling point; the input signal and the output signal have frequencies in a terahertz frequency range; and the system is fabricated as a monolithic integrated structure having the waveguide structure fabricated by micromachining and the circuit fabricated monolithically.Type: ApplicationFiled: August 29, 2009Publication date: March 3, 2011Inventors: William Roland Deal, Kevin Masaru Kung Hoong Leong, Vesna Radisic, Patty Pei-Ling Chang-Chien, Richard Lai
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Patent number: 7777318Abstract: A wafer-level package that employs one or more integrated hydrogen getters within the wafer-level package on a substrate wafer or a cover wafer. The hydrogen getters are provided between and among the integrated circuits on the substrate wafer or the cover wafer, and are deposited during the integrated circuit fabrication process. In one non-limiting embodiment, the substrate wafer is a group III-V semiconductor material, and the hydrogen getter includes a titanium layer, a nickel layer, and a palladium layer.Type: GrantFiled: July 24, 2007Date of Patent: August 17, 2010Assignee: Northrop Grumman Systems CorporationInventors: Kelly Jill Tornquist Hennig, Patty Pei-Ling Chang-Chien, Xianglin Zeng, Jeffrey Ming-Jer Yang
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Patent number: 7696062Abstract: A method for mounting a dielectric substrate to a semiconductor substrate, such as mounting a dielectric antenna substrate to an MMIC semiconductor substrate. The method includes providing a thin dielectric antenna substrate having metallized layers on opposing sides. In one embodiment, carrier wafers are used to handle and maintain the dielectric substrate in a flat configuration as the metallized layers are patterned. The dielectric substrate is sealed to the semiconductor substrate using a low temperature bonding process. In an alternate embodiment, the metallized layers on the dielectric substrate are patterned simultaneously so as to prevent the substrate from curling.Type: GrantFiled: July 25, 2007Date of Patent: April 13, 2010Assignee: Northrop Grumman Systems CorporationInventors: Patty Pei-Ling Chang-Chien, Chi Kong Cheung, Melanie Sachiko Yajima, Xianglin Zeng
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Patent number: 7662669Abstract: A method for fabricating wafer-level packages including lateral interconnects. The method includes precutting a cover wafer at the locations where the cover wafer will be completely cut through to separate the wafer-level packages. The cover wafer is bonded to the substrate wafer using bonding rings so as to seal the integrated circuit within a cavity between the cover wafer and the substrate wafer, where the precuts face the substrate wafer. The cover wafer is then cut at the precut locations to remove the unwanted portions of the cover wafer between the packages and expose contacts or probe pads for the lateral interconnects. The substrate wafer is then cut between the wafer-level packages to separate the packages.Type: GrantFiled: July 24, 2007Date of Patent: February 16, 2010Assignee: Northrop Grumman Space & Mission Systems Corp.Inventors: Patty Pei-Ling Chang-Chien, Kelly Jill Tornquist Hennig, Ken Wai-Kin Ho, Ann Kent-Ming Ho
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Publication number: 20090026627Abstract: A semiconductor structure, such as a wafer-level package or a vertically stacked structure. The wafer-level package includes a substrate wafer on which an integrated circuit is formed. A cover wafer is bonded to the substrate wafer to provide a cavity between the substrate wafer and the cover wafer in which the integrated circuit is hermetically sealed. Vias are formed through the substrate wafer and make electrical contact with signal and ground traces formed on the substrate wafer within the cavity, where the traces are electrically coupled to the integrated circuit. Probe pads are formed on the substrate wafer outside of the cavity and are in electrical contact with the vias. A support post is provided directly beneath the probe pad so that when pressure is applied to the probe pad from the probe for testing purposes, the support post prevents the substrate wafer from flexing and being damaged.Type: ApplicationFiled: July 24, 2007Publication date: January 29, 2009Applicant: Northrop Grumman Space & Mission Systems Corp.Inventors: Patty Pei-Ling Chang-Chien, Kelly Jill Tornquist Hennig
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Publication number: 20090029526Abstract: A method for fabricating wafer-level packages including lateral interconnects. The method includes precutting a cover wafer at the locations where the cover wafer will be completely cut through to separate the wafer-level packages. The cover wafer is bonded to the substrate wafer using bonding rings so as to seal the integrated circuit within a cavity between the cover wafer and the substrate wafer, where the precuts face the substrate wafer. The cover wafer is then cut at the precut locations to remove the unwanted portions of the cover wafer between the packages and expose contacts or probe pads for the lateral interconnects. The substrate wafer is then cut between the wafer-level packages to separate the packages.Type: ApplicationFiled: July 24, 2007Publication date: January 29, 2009Applicant: Northrop Grumman Space & Mission Systems Corp.Inventors: Patty Pei-Ling Chang-Chien, Kelly Jill Tornquist Hennig, Ken Wai-Kin Ho, Ann Kent-Ming Ho
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Publication number: 20090026598Abstract: A wafer-level package that employs one or more integrated hydrogen getters within the wafer-level package on a substrate wafer or a cover wafer. The hydrogen getters are provided between and among the integrated circuits on the substrate wafer or the cover wafer, and are deposited during the integrated circuit fabrication process. In one non-limiting embodiment, the substrate wafer is a group III-V semiconductor material, and the hydrogen getter includes a titanium layer, a nickel layer, and a palladium layer.Type: ApplicationFiled: July 24, 2007Publication date: January 29, 2009Applicant: Northrop Grumman Space & Mission Systems Corp.Inventors: Kelly Jill Tornquist Hennig, Patty Pei-Ling Chang-Chien, Xianglin Zeng, Jeffrey Ming-Jer Yang
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Publication number: 20090029554Abstract: A method for mounting a dielectric substrate to a semiconductor substrate, such as mounting a dielectric antenna substrate to an MMIC semiconductor substrate. The method includes providing a thin dielectric antenna substrate having metallized layers on opposing sides. In one embodiment, carrier wafers are used to handle and maintain the dielectric substrate in a flat configuration as the metallized layers are patterned. The dielectric substrate is sealed to the semiconductor substrate using a low temperature bonding process. In an alternate embodiment, the metallized layers on the dielectric substrate are patterned simultaneously so as to prevent the substrate from curling.Type: ApplicationFiled: July 25, 2007Publication date: January 29, 2009Applicant: Northrop Grumman Space & Mission Systems Corp.Inventors: Patty Pei-Ling Chang-Chien, Chi Kong Cheung, Melanie Sachiko Yajima, Xianglin Zeng