Abstract: An automobile head unit display system including an antenna, a lightbox assembly and a circuit board is described therein. The antenna is attached to the lightbox system, while the lightbox assembly is attached to the circuit board. The antenna and the lightbox assembly are in communication with the circuit board.

Abstract: A System including device access, network access system management, and related method for providing users who have require aperiodic high bandwidth data transmission requirements between remote sites access over a public switched digital network of a conventional type is disclosed. The invention uses a scheme of inverse multiplexing by which it first logically splits a high bandwidth information stream into multiple narrow band signals for transmission through public switched digital network over a plurality of narrow band channels to be received at the remote location by another Switched Network Access System then recombined to form the original high bandwidth information stream causing the multiple narrow band channels to appear as a single high bandwidth channel to remote high bandwidth end users.

Abstract: A dual-tracking phase-locked loop circuit is provided for moving with minimum disruption from conventional PLL operation to processor-controlled tracking of another closely related clock. In addition to conventional PLL components the circuit comprises a processor-controlled up/down counter which may operate alternatively as a link in the loop or as providing the base-line frequency determining value at the time of transition from PLL to processor-controlled tracking operation, thereby ensuring none disruptive transition.

Abstract: A bus interface for interfacing between a processor and a shared bus is disclosed. The bus interface allows the exchange of data in the form of packets between the bus and the processor. An interface control device exchanges control data with the shared bus (e.g. identification signals, polling signals, control signals) in order to regulate accesses of the interface circuit to the shared bus. State machines (e.g. a transmitter and a receiver) including data pipelines, are responsive to control signals from the interface control device for exchanging data between the shared bus and a data storage device. An access control device both controls the flow of data between the processor and the data storage device and regulates access to the data storage device between the processor and the state machines.