Patents by Inventor Paul A. Drake
Paul A. Drake has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11968309Abstract: Methods and systems for authenticating operations of an aircraft are disclosed. In at least one embodiment, the method may include: receiving, by an aircraft data gateway, a request for an operation of an aircraft from an operations portal; performing a first digital authentication of the request using first digital authentication information; performing a second digital authentication of the request using second digital authentication information, the second digital authentication information being distinct from the first digital authentication information; and executing the operation of the aircraft upon validating the first digital authentication and the second digital authentication.Type: GrantFiled: October 16, 2020Date of Patent: April 23, 2024Assignee: HONEYWELL INTERNATIONAL INC.Inventors: Vijayshankaran Iyer, Phani Ammi Raju Pothula, Kovalan Ramana, G V Bharath Kumar, Raveendra Reddy Mudimala, Paul Drake, Lawrence Marsala
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Patent number: 11923327Abstract: A silicon integrated circuit. In some embodiments, the silicon integrated circuit includes a first conductive trace, on a top surface of the silicon integrated circuit, a dielectric layer, on the first conductive trace, and a second conductive trace, on the dielectric layer, connected to the first conductive trace through a first via.Type: GrantFiled: June 5, 2020Date of Patent: March 5, 2024Assignee: Rockley Photonics LimitedInventors: Michael Lee, John Paul Drake, Ying Luo, Vivek Raghunathan, Brett Sawyer
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Publication number: 20240053551Abstract: A wafer with a buried V-groove cavity, and a method for fabricating V-grooves. In some embodiments, the method includes bonding a first layer, to a top surface of a substrate, to form a composite wafer, the first layer being composed of a first semiconductor material, the substrate being composed of a second semiconductor material, the top surface of the substrate having a cavity, the cavity including a V-groove.Type: ApplicationFiled: December 10, 2021Publication date: February 15, 2024Inventors: Janne Ikonen, John Paul Drake, Henri Nykänen, Damiana Lerose
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Publication number: 20230411427Abstract: A method of eliminating interconnect strains in a stack-up is provided. The method includes providing a detector portion including a detector substrate and detector layers, providing a read-out integrated circuit (ROIC) stack-up including ROIC layers and an initial ROIC substrate, removing the initial ROIC substrate from the ROIC layers, attaching a new ROIC substrate to a first surface of the ROIC layers, the new ROIC substrate having a coefficient of thermal expansion (CTE) that matches a CTE of the detector substrate and hybridizing the detector layers to a second surface of the ROIC layers by way of interconnects.Type: ApplicationFiled: August 30, 2023Publication date: December 21, 2023Inventors: Paul A. Drake, Christopher Moshenrose, Heather D. Leifeste
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Patent number: 11776981Abstract: A method of eliminating interconnect strains in a stack-up is provided. The method includes providing a detector portion including a detector substrate and detector layers, providing a read-out integrated circuit (ROIC) stack-up including ROIC layers and an initial ROIC substrate, removing the initial ROIC substrate from the ROIC layers, attaching a new ROIC substrate to a first surface of the ROIC layers, the new ROIC substrate having a coefficient of thermal expansion (CTE) that matches a CTE of the detector substrate and hybridizing the detector layers to a second surface of the ROIC layers by way of interconnects.Type: GrantFiled: November 18, 2020Date of Patent: October 3, 2023Assignee: RAYTHEON COMPANYInventors: Paul A. Drake, Christopher Moshenrose, Heather D. Leifeste
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Patent number: 11513292Abstract: A mirror and method of fabricating the mirror, the method comprising: providing a silicon-on-insulator substrate, the substrate comprising: a silicon support layer; a buried oxide (BOX) layer on top of the silicon support layer; and a silicon device layer on top of the BOX layer; creating a via in the silicon device layer, the via extending to the BOX layer; etching away a portion of the BOX layer starting at the via and extending laterally away from the via in a first direction to create a channel between the silicon device layer and silicon support layer; applying an anisotropic etch via the channel to regions of the silicon device layer and silicon support layer adjacent to the channel; the anisotropic etch following an orientation plane of the silicon device layer and silicon support layer to create a cavity underneath an overhanging portion of the silicon device layer; the overhanging portion defining a planar underside surface for vertically coupling light into and out of the silicon device layer; andType: GrantFiled: May 4, 2020Date of Patent: November 29, 2022Inventors: Henri Nykänen, John Paul Drake, Evie Kho, Damiana Lerose, Sanna Leena Mäkelä, Amit Singh Nagra
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Publication number: 20220310540Abstract: A silicon integrated circuit. In some embodiments, the silicon integrated circuit includes a first conductive trace, on a top surface of the silicon integrated circuit, a dielectric layer, on the first conductive trace, and a second conductive trace, on the dielectric layer, connected to the first conductive trace through a first via.Type: ApplicationFiled: June 5, 2020Publication date: September 29, 2022Inventors: Michael LEE, John Paul DRAKE, Ying LUO, Vivek RAGHUNATHAN, Brett SAWYER
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Publication number: 20220157874Abstract: A method of eliminating interconnect strains in a stack-up is provided. The method includes providing a detector portion including a detector substrate and detector layers, providing a read-out integrated circuit (ROIC) stack-up including ROIC layers and an initial ROIC substrate, removing the initial ROIC substrate from the ROIC layers, attaching a new ROIC substrate to a first surface of the ROIC layers, the new ROIC substrate having a coefficient of thermal expansion (CTE) that matches a CTE of the detector substrate and hybridizing the detector layers to a second surface of the ROIC layers by way of interconnects.Type: ApplicationFiled: November 18, 2020Publication date: May 19, 2022Inventors: Paul A. Drake, Christopher Moshenrose, Heather D. Leifeste
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Publication number: 20220051571Abstract: Methods and systems for authenticating operations of an aircraft are disclosed. In at least one embodiment, the method may include: receiving, by an aircraft data gateway, a request for an operation of an aircraft from an operations portal; performing a first digital authentication of the request using first digital authentication information; performing a second digital authentication of the request using second digital authentication information, the second digital authentication information being distinct from the first digital authentication information; and executing the operation of the aircraft upon validating the first digital authentication and the second digital authentication.Type: ApplicationFiled: October 16, 2020Publication date: February 17, 2022Inventors: Vijayshankaran IYER, Phani Ammi Raju POTHULA, Kovalan RAMANA, G V Bharath Kumar, Raveendra Reddy MUDIMALA, Paul DRAKE, Lawrence MARSALA
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Patent number: 10754438Abstract: The various implementations described herein include systems, methods and/or devices used to enable false touch detection. An exemplary method is performed at a touch-sensitive device and includes performing a plurality of scans of the touch-sensitive array during a time window, response data is captured from each of the plurality of scans. Distilling a value for each respective scan from the response data captured during the respective scan. Identifying a set of peaks from the distilled values, each peak having a plurality of characteristic values. The method further includes: (i) determining a metric for the peaks based on the plurality of characteristic values associated with each peak; (ii) determining whether the metric satisfies a criterion, and (iii) in response to determining that the metric satisfies the criterion, rejecting at least some of the response data captured during the time window as representing at least one false touch.Type: GrantFiled: August 11, 2017Date of Patent: August 25, 2020Assignee: PARADE TECHNOLOGIES, LTD.Inventors: Jeffrey Tucker, Victor Paul Drake, Jeffrey Jay Dahlin, Kevin Ryan McNeely
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Publication number: 20200264372Abstract: A mirror and method of fabricating the mirror, the method comprising: providing a silicon-on-insulator substrate, the substrate comprising: a silicon support layer; a buried oxide (BOX) layer on top of the silicon support layer; and a silicon device layer on top of the BOX layer; creating a via in the silicon device layer, the via extending to the BOX layer; etching away a portion of the BOX layer starting at the via and extending laterally away from the via in a first direction to create a channel between the silicon device layer and silicon support layer; applying an anisotropic etch via the channel to regions of the silicon device layer and silicon support layer adjacent to the channel; the anisotropic etch following an orientation plane of the silicon device layer and silicon support layer to create a cavity underneath an overhanging portion of the silicon device layer; the overhanging portion defining a planar underside surface for vertically coupling light into and out of the silicon device layer; and aType: ApplicationFiled: May 4, 2020Publication date: August 20, 2020Inventors: Henri Nykänen, John Paul Drake, Evie Kho, Damiana Lerose, Sanna Leena Mäkelä, Amit Singh Nagra
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Patent number: 10641962Abstract: A mirror and method of fabricating the mirror, the method comprising: providing a silicon-on-insulator substrate, the substrate comprising: a silicon support layer; a buried oxide (BOX) layer on top of the silicon support layer; and a silicon device layer on top of the BOX layer; creating a via in the silicon device layer, the via extending to the BOX layer; etching away a portion of the BOX layer starting at the via and extending laterally away from the via in a first direction to create a channel between the silicon device layer and silicon support layer; applying an anisotropic etch via the channel to regions of the silicon device layer and silicon support layer adjacent to the channel; the anisotropic etch following an orientation plane of the silicon device layer and silicon support layer to create a cavity underneath an overhanging portion of the silicon device layer; the overhanging portion defining a planar underside surface for vertically coupling light into and out of the silicon device layer; and aType: GrantFiled: March 28, 2019Date of Patent: May 5, 2020Assignee: Rockley Photonics LimitedInventors: Henri Nykänen, John Paul Drake, Evie Kho, Damiana Lerose, Sanna Leena Mäkelä, Amit Singh Nagra
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Patent number: 10475664Abstract: In one aspect, a method includes heating a wafer chuck, heating a first wafer, depositing a first epoxy along at least a portion of a surface of the first wafer disposed on the wafer chuck, spinning the wafer chuck to spread the first epoxy at least partially across the first wafer, placing a second wafer on the first epoxy disposed on the first wafer and bonding the second wafer to the first epoxy under vacuum to form a two-wafer-bonded structure.Type: GrantFiled: November 22, 2017Date of Patent: November 12, 2019Assignee: RAYTHEON COMPANYInventors: Andrew Cahill, Jonathan Getty, Daniel D. Lofgreen, Paul A. Drake
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Publication number: 20190302366Abstract: A mirror and method of fabricating the mirror, the method comprising: providing a silicon-on-insulator substrate, the substrate comprising: a silicon support layer; a buried oxide (BOX) layer on top of the silicon support layer; and a silicon device layer on top of the BOX layer; creating a via in the silicon device layer, the via extending to the BOX layer; etching away a portion of the BOX layer starting at the via and extending laterally away from the via in a first direction to create a channel between the silicon device layer and silicon support layer; applying an anisotropic etch via the channel to regions of the silicon device layer and silicon support layer adjacent to the channel; the anisotropic etch following an orientation plane of the silicon device layer and silicon support layer to create a cavity underneath an overhanging portion of the silicon device layer; the overhanging portion defining a planar underside surface for vertically coupling light into and out of the silicon device layer; and aType: ApplicationFiled: March 28, 2019Publication date: October 3, 2019Inventors: Henri Nykänen, John Paul Drake, Evie Kho, Damiana Lerose, Sanna Leena Mäkelä, Amit Singh Nagra
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Patent number: 10372266Abstract: An exemplary method used to improve water detection on a touch-sensitive display includes performing a plurality of scans of a touch-sensitive array using at least two different scan patterns to capture response data for at least a subset of the plurality of sensor electrodes. The method further includes determining a signal direction for each sensor electrode in the subset using the response data. The method further includes identifying touch zone(s), each comprising a group of sensor electrodes with signal directions that point towards a peak electrode response included in the group. The peak electrode response indicates a location of a candidate touch object on the touch-sensitive array. For each identified touch zone, reporting a touch object at the location of the peak electrode response upon determination that the peak electrode response for the touch zone satisfies a predefined response threshold.Type: GrantFiled: July 10, 2017Date of Patent: August 6, 2019Assignee: PARADE TECHNOLOGIES, LTD.Inventor: Victor Paul Drake
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Patent number: 10162465Abstract: A method is performed at a touch sensing system that includes a two-dimensional capacitive sense array. The process measures the capacitance of the capacitive sensors, and identifies a first sensor whose measured capacitance is a local peak. The local peak is within a local rectangular array. The process computes column sums for each column of the rectangular array and determines whether to apply a smoothing algorithm. When the smoothing algorithm is not applied, the process computes an x-coordinate of a touch using a plurality of the column sums. When applying the smoothing algorithm, the process computes the x-coordinate of the touch as an average of two x-coordinate calculations. Each of the two x-coordinate calculations conditionally performs a horizontal shift of the local rectangular array based on comparing the peak measured capacitance to an adjacent measured capacitance and computes a respective x-coordinate using a respective plurality of the column sums.Type: GrantFiled: July 27, 2016Date of Patent: December 25, 2018Assignee: PARADE TECHNOLOGIES, LTD.Inventor: Victor Paul Drake
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Publication number: 20180335889Abstract: The various implementations described herein include systems, methods and/or devices used to enable false touch detection. An exemplary method is performed at a touch-sensitive device and includes performing a plurality of scans of the touch-sensitive array during a time window, response data is captured from each of the plurality of scans. Distilling a value for each respective scan from the response data captured during the respective scan. Identifying a set of peaks from the distilled values, each peak having a plurality of characteristic values. The method further includes: (i) determining a metric for the peaks based on the plurality of characteristic values associated with each peak; (ii) determining whether the metric satisfies a criterion, and (iii) in response to determining that the metric satisfies the criterion, rejecting at least some of the response data captured during the time window as representing at least one false touch.Type: ApplicationFiled: August 11, 2017Publication date: November 22, 2018Inventors: Jeffrey Tucker, Victor Paul Drake, Jeffrey Jay Dahlin, Kevin Ryan McNeely
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Publication number: 20180275825Abstract: The various implementations described herein include systems, methods and/or devices used to improve water detection on a touch-sensitive display. An exemplary method includes performing a plurality of scans of a touch-sensitive array using at least two different scan patterns to capture response data for at least a subset of the plurality of sensor electrodes. The method further includes determining a signal direction for each sensor electrode in the subset using the response data. The method further includes identifying touch zone(s), each comprising a group of sensor electrodes with signal directions that point towards a peak electrode response included in the group. The peak electrode response indicates a location of a candidate touch object on the touch-sensitive array. For each identified touch zone, reporting a touch object at the location of the peak electrode response upon determination that the peak electrode response for the touch zone satisfies a predefined response threshold.Type: ApplicationFiled: July 10, 2017Publication date: September 27, 2018Inventor: Victor Paul Drake
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Patent number: 9995604Abstract: An optical sensor (10) comprises an optical cavity defined by a dielectric body and responsive to one or more physical environmental conditions, and a waveguide (70) having a terminal end spaced apart from the optical cavity such that light is optically coupled from the terminal end of the waveguide (70) to the optical cavity. The waveguide (70) is arranged such that, in use, it is maintained at a first temperature that would not damage the optical coupling to the optical cavity when the dielectric body is maintained at a second temperature sufficient to damage the optical coupling to the optical cavity.Type: GrantFiled: July 5, 2016Date of Patent: June 12, 2018Assignee: OXSENSIS LIMITEDInventors: Arnold Peter Roscoe Harpin, John Paul Drake, Stephen Geoffrey Tyler
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Publication number: 20180096833Abstract: In one aspect, a method includes heating a wafer chuck, heating a first wafer, depositing a first epoxy along at least a portion of a surface of the first wafer disposed on the wafer chuck, spinning the wafer chuck to spread the first epoxy at least partially across the first wafer, placing a second wafer on the first epoxy disposed on the first wafer and bonding the second wafer to the first epoxy under vacuum to form a two-wafer-bonded structure.Type: ApplicationFiled: November 22, 2017Publication date: April 5, 2018Applicant: Raytheon CompanyInventors: Andrew Cahill, Jonathan Getty, Daniel D. Lofgreen, Paul A. Drake