Patents by Inventor Paul A. Hoover
Paul A. Hoover has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11958033Abstract: This invention relates to modified MOF materials, methods of preparing them and processes using them. A modified MOF of the invention is modified by impregnating a MOF with an inorganic metal salt. The starting MOF contains at least one linker or ligand which contains an aryl amino group as part of its structure. These modified MOFs are able to adsorb either basic or acidic toxic industrial compounds (TIC). The modified MOFs can be used to remove TICs from various gaseous streams such as air.Type: GrantFiled: March 30, 2021Date of Patent: April 16, 2024Assignee: NuMat Technologies, Inc.Inventors: Mitchell Hugh Weston, William Morris, William Joseph Hoover, Patrick Emmett Fuller, John Paul Siegfried, Randi Danielle Groy, Jeffrey Loren Wells, Timothy Chiaan Wang, Edwin Alfonso Argueta Fajardo
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Publication number: 20240113974Abstract: Mobile management method, system and client. Method includes receiving a DNS query for a host name from an application on client; retrieving reputation data associated with host name from a local cache on client; and determining a policy based on host name and the reputation data. Based on determined policy for the host name, blocking attempted network flows to a host corresponding to host name to produce blocked attempted network flows. Method also includes sending attempted network flow metadata related to the blocked attempted network flows to a collector on client; transmitting the attempted network flow metadata from the collector to a VPN server pool via a VPN tunnel; and producing an anomaly report from the transmitted attempted network flow metadata. The anomaly report includes at least one of anomalies, cohorts, trends, location boundaries, detected network security issues, detected compromised clients and/or optimized network usage.Type: ApplicationFiled: November 30, 2023Publication date: April 4, 2024Applicant: MOBILE SONIC, INC.Inventors: Joseph T. SAVARESE, Steven HECKT, Michael E. BRYANT, Eric C. MCNEILL, Carter SMITH, Elizabeth KIHSLINGER, Thomas Gunther HELMS, Camilla KEENAN-KOCH, Joseph G. SOUZA, Paul HOOVER, S. Aaron STAVENS, Christian E. HOFSTAEDTER, Jonathan SCOTT, Erik OLSON, James Scott SIMPKINS, Stephen Gregory FALLIN, John Harvey HILLOCK, Eivind NAESS, Michael Lee SNYDER, David Michael MIRLY, Marius LEE, Glenn Patrick ARANAS, Norman C. HAMER, Tridib DUTTA, Andrew James HOOVER, Thomas A. SWEET, Mark ANACKER, An PHAN
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Publication number: 20240048493Abstract: Mobile management method, system and client. The method includes receiving a DNS query for a host name from an application on a client; retrieving reputation data associated with the host name from a local cache on the client; determining a policy for the host name, which is associated with the host name and the reputation data associated with the host name; based on the determined policy for the host name, blocking attempted network flows to a host corresponding to the host name; sending at least attempted network flow metadata related to the blocked attempted network flows to a collector on the client; and transmitting the attempted network flow metadata in the collector to a VPN server pool via a VPN tunnel.Type: ApplicationFiled: January 27, 2023Publication date: February 8, 2024Applicant: MOBILE SONIC, INC.Inventors: Joseph T. SAVARESE, Steven HECKT, Michael E. BRYANT, Eric C. MCNEILL, Carter SMITH, Elizabeth KIHSLINGER, Thomas Gunther HELMS, Camilla KEENAN-KOCH, Joseph G. SOUZA, Paul HOOVER, S. Aaron STAVENS, Christian E. HOFSTAEDTER, Jonathan SCOTT, Erik OLSON, James Scott SIMPKINS, Stephen Gregory FALLIN, John Harvey HILLOCK, Eivind NAESS, Michael Lee SNYDER, David Michael MIRLY, Marius LEE, Glenn Patrick ARANAS, Norman C. HAMER, Tridib DUTTA, Andrew James HOOVER, Thomas A. SWEET, Mark ANACKER, An PHAN
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Patent number: 11623358Abstract: A sheath has a sheath body having a front plate and a back plate spaced apart from the front plate. The front plate and back plate define a cavity within the sheath body. The cavity is externally accessible through an opening formed between the front plate and the back plate. Snapping fasteners are positioned about a front side and a back side of the back plate. The snapping fasteners each include a male component and a female component. The male component and female component of each fastener are mounted on opposite sides of the back plate. The male component includes a protrusion extending away from the sheath body. The female component defines a recess that is complimentary to the protrusion.Type: GrantFiled: May 18, 2020Date of Patent: April 11, 2023Assignee: FISKARS BRANDS, INC.Inventors: Patrick Hunt, Gregory Shulman, Paul Hoover
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Patent number: 11595312Abstract: Mobile management method and system. The method includes receiving from an application on a client a DNS query for a host name; retrieving reputation data associated with the host name from a local cache on the client; determining whether a policy associated with the host name and the reputation data associated with the host name exists; and one of: sending network flows one of: through a VPN tunnel to a server or out a local proxy on the client to a private or public network; or blocking the network flow based on the determined policy for the host name.Type: GrantFiled: April 14, 2021Date of Patent: February 28, 2023Assignee: MOBILE SONIC, INC.Inventors: Joseph T. Savarese, Steven Heckt, Michael E. Bryant, Eric C. McNeill, Carter Smith, Elizabeth Kihslinger, Thomas Gunther Helms, Camilla Keenan-Koch, Joseph G. Souza, Paul Hoover, S. Aaron Stavens, Christian E. Hofstaedter, Jonathan Scott, Erik Olson, James Scott Simpkins, Stephen Gregory Fallin, John Harvey Hillock, Eivind Naess, Michael Lee Snyder, David Michael Mirly, Marius Lee, Glenn Patrick Aranas, Norman C. Hamer, Tridib Dutta, Andrew James Hoover, Thomas A. Sweet, Mark Anacker, An Phan
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Patent number: 11256846Abstract: A computer implemented method for analyzing a timing of an integrated circuit, wherein an interconnection of a first net of the integrated circuit includes at least one conducting segment formed in a wiring layer or a via layer, includes obtaining a plurality of resistances and a plurality of capacitances, which correspond to each of the at least one conducting segment, based on a process variation, counting a number of layers in which the at least one conducting segments is formed, and calculating a corner resistance and a corner capacitance of the first net, based on the number of layers, the plurality of resistances, and the plurality of capacitances, wherein the counting of the number of layers includes calculating an effective number of layers based on a resistance variability and/or a capacitance variability of each of the layers.Type: GrantFiled: May 7, 2019Date of Patent: February 22, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Moon-Su Kim, Naya Ha, Jong-Ku Kang, Andrew Paul Hoover
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Publication number: 20210320871Abstract: Mobile management method and system. The method includes receiving from an application on a client a DNS query for a host name; retrieving reputation data associated with the host name from a local cache on the client; determining whether a policy associated with the host name and the reputation data associated with the host name exists; and one of: sending network flows one of: through a VPN tunnel to a server or out a local proxy on the client to a private or public network; or blocking the network flow based on the determined policy for the host name.Type: ApplicationFiled: April 14, 2021Publication date: October 14, 2021Applicant: NETMOTION SOFTWARE, INC.Inventors: Joseph T. SAVARESE, Steven HECKT, Michael E. BRYANT, Eric C. MCNEILL, Carter SMITH, Elizabeth KIHSLINGER, Thomas Gunther HELMS, Camilla KEENAN-KOCH, Joseph G. SOUZA, Paul HOOVER, Scott A. STAVENS, Christian E. HOFSTAEDTER, Jonathan SCOTT, Erik OLSON, James Scott SIMPKINS, Stephen Gregory FALLIN, John Harvey HILLOCK, Eivind NAESS, Michael Lee SNYDER, David Michael MIRLY, Marius LEE, Glenn Patrick ARANAS, Norman C. HAMER, Tridib DUTTA, Andrew James HOOVER, Thomas A. SWEET, Mark ANACKER, An PHAN
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Publication number: 20200384662Abstract: A sheath has a sheath body having a front plate and a back plate spaced apart from the front plate. The front plate and back plate define a cavity within the sheath body. The cavity is externally accessible through an opening formed between the front plate and the back plate. Snapping fasteners are positioned about a front side and a back side of the back plate. The snapping fasteners each include a male component and a female component. The male component and female component of each fastener are mounted on opposite sides of the back plate. The male component includes a protrusion extending away from the sheath body. The female component defines a recess that is complimentary to the protrusion.Type: ApplicationFiled: May 18, 2020Publication date: December 10, 2020Applicant: Fiskars Brands, Inc.Inventors: Patrick Hunt, Gregory Shulman, Paul Hoover
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Patent number: 10784198Abstract: A semiconductor integrated circuit including a substrate, a series of metal layers, and a series of insulating layers. The metal layers and the insulating layers are alternately arranged in a stack on the substrate. The semiconductor integrated circuit also includes at least two standard cells in the substrate and at least one power rail crossing over boundaries of the at least two standard cells. The power rail includes a vertical section of conductive material extending continuously through at least two vertical levels of the stack. The two vertical levels of the stack include one metal layer and one insulating layer. The insulating layer is above the metal layer.Type: GrantFiled: August 18, 2017Date of Patent: September 22, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Rwik Sengupta, Andrew Paul Hoover, Matthew Berzins, Sam Tower, Mark S. Rodder
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Patent number: 10748889Abstract: According to one general aspect, an apparatus may include a metal layer having a metal pitch between metal elements, and a gate electrode layer having a gate pitch between gate electrode elements, wherein the gate electrode pitch is a ratio of the metal pitch. The apparatus may include at least two power rails coupled, by via staples, with the metal layer, wherein the via staples at least partially overlap one or more of the gate electrode elements. The apparatus may include even and odd pluralities of standard cells, each respectively located in even/odd placement sites wherein portions of the standard cells that carry signals within the metal layer do not connect to the via staples.Type: GrantFiled: February 12, 2019Date of Patent: August 18, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Matthew Berzins, Andrew Paul Hoover, Christopher Alan Peura
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Publication number: 20190385999Abstract: According to one general aspect, an apparatus may include a metal layer having a metal pitch between metal elements, and a gate electrode layer having a gate pitch between gate electrode elements, wherein the gate electrode pitch is a ratio of the metal pitch. The apparatus may include at least two power rails coupled, by via staples, with the metal layer, wherein the via staples at least partially overlap one or more of the gate electrode elements. The apparatus may include even and odd pluralities of standard cells, each respectively located in even/odd placement sites wherein portions of the standard cells that carry signals within the metal layer do not connect to the via staples.Type: ApplicationFiled: February 12, 2019Publication date: December 19, 2019Inventors: Matthew BERZINS, Andrew Paul HOOVER, Christopher Alan PEURA
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Patent number: 10430537Abstract: According to an example embodiment, an integrated circuit may include a plurality of cells and a plurality of paths that supply power to the plurality of cells, respectively. The plurality of cells and the plurality of paths may be arranged based on a plurality of propagation delays of the plurality of cells, which include a plurality of first delays of the plurality of cells generated by a plurality of power resistances of the plurality of paths and a plurality of second delays of the plurality of cells generated based on a plurality of arrival timing windows that overlap each other.Type: GrantFiled: May 2, 2018Date of Patent: October 1, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Jongyoon Jung, Andrew Paul Hoover
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Publication number: 20190258775Abstract: A computer implemented method for analyzing a timing of an integrated circuit, wherein an interconnection of a first net of the integrated circuit includes at least one conducting segment formed in a wiring layer or a via layer, includes obtaining a plurality of resistances and a plurality of capacitances, which correspond to each of the at least one conducting segment, based on a process variation, counting a number of layers in which the at least one conducting segments is formed, and calculating a corner resistance and a corner capacitance of the first net, based on the number of layers, the plurality of resistances, and the plurality of capacitances, wherein the counting of the number of layers includes calculating an effective number of layers based on a resistance variability and/or a capacitance variability of each of the layers.Type: ApplicationFiled: May 7, 2019Publication date: August 22, 2019Inventors: MOON-SU KIM, Naya Ha, Jong-ku Kang, Andrew Paul Hoover
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Patent number: 10372869Abstract: A method of analyzing an integrated circuit, which is implemented by a computing system or a processor, wherein an interconnection of a first net of the integrated circuit includes at least one conducting segment corresponding to one wiring layer or one via, includes receiving a plurality of resistances and a plurality of capacitances, which correspond to the first net, based on a process variation, counting a number of conducting segments corresponding to the first net, and calculating a first resistance or a first capacitance of the first net, based on the number of conducting segments, the plurality of resistances, and the plurality of capacitances.Type: GrantFiled: March 25, 2016Date of Patent: August 6, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Moon-Su Kim, Naya Ha, Jong-Ku Kang, Andrew Paul Hoover
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Publication number: 20190151032Abstract: A system comprises a teleoperational assembly including a teleoperational manipulator coupled to a plurality of instruments in a surgical environment. The system also comprises a processing unit including one or more processors. The processing unit is configured to display a first synthetic rendering of the plurality of instruments, recognize a triggering event, and change from displaying the first synthetic rendering to displaying a second synthetic rendering of the plurality of instruments in response to recognition of the triggering event.Type: ApplicationFiled: April 25, 2017Publication date: May 23, 2019Inventors: Tabish Mustufa, Benjamin S. Flamm, Paul A. Hoover
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Publication number: 20180322233Abstract: According to an example embodiment, an integrated circuit may include a plurality of cells and a plurality of paths that supply power to the plurality of cells, respectively. The plurality of cells and the plurality of paths may be arranged based on a plurality of propagation delays of the plurality of cells, which include a plurality of first delays of the plurality of cells generated by a plurality of power resistances of the plurality of paths and a plurality of second delays of the plurality of cells generated based on a plurality of arrival timing windows that overlap each other.Type: ApplicationFiled: May 2, 2018Publication date: November 8, 2018Inventors: Jongyoon Jung, Andrew Paul Hoover
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Publication number: 20180269152Abstract: A semiconductor integrated circuit including a substrate, a series of metal layers, and a series of insulating layers. The metal layers and the insulating layers are alternately arranged in a stack on the substrate. The semiconductor integrated circuit also includes at least two standard cells in the substrate and at least one power rail crossing over boundaries of the at least two standard cells. The power rail includes a vertical section of conductive material extending continuously through at least two vertical levels of the stack. The two vertical levels of the stack include one metal layer and one insulating layer. The insulating layer is above the metal layer.Type: ApplicationFiled: August 18, 2017Publication date: September 20, 2018Inventors: Rwik Sengupta, Andrew Paul Hoover, Matthew Berzins, Sam Tower, Mark S. Rodder
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Patent number: 10003576Abstract: Techniques for determining which resource access requests are handled locally at a remote computer, and which resource access requests are routed or “redirected” through a virtual private network. One or more routing or “redirection” rules are downloaded from a redirection rule server to a remote computer. When the node of the virtual private network running on the remote computer receives a resource access request, it compares the identified resource with the rules. Based upon how the identified resource matches one or more rules, the node will determine whether the resource access request is redirected through the virtual private network or handled locally (e.g., retrieved locally from another network). A single set of redirection rules can be distributed to and employed by a variety of different virtual private network communication techniques.Type: GrantFiled: June 13, 2016Date of Patent: June 19, 2018Assignee: SONICWALL INC.Inventors: Chris Hopen, Bryan Sauve, Paul Hoover, Bill Perry
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Patent number: 9904758Abstract: According to one general aspect, a method may include receiving a circuit model that includes logic circuits that are represented by respective cells. The method may include providing a timing adjustment to the circuit model. This providing may include determining one or more respective cells that are candidates for adjustment by employing a sub-micron stress effect, and, for each candidate, replacing a candidate cell with a stressed cell, wherein a candidate cell and stressed cell perform a same logical function. Each stressed cell may include: a gate electrode, a first gate-cut shape disposed to cut the gate electrode, wherein the first gate-cut shape is disposed upon a row-boundary, a second gate-cut shape disposed upon the row-boundary, a gate-cut break disposed between the first gate-cut shape and the second gate-cut shape, an active region, and an active-cut shape disposed to cut the active region.Type: GrantFiled: July 12, 2016Date of Patent: February 27, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Matthew Berzins, Andrew Paul Hoover
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Publication number: 20170337320Abstract: According to one general aspect, a method may include receiving a circuit model that includes logic circuits that are represented by respective cells. The method may include providing a timing adjustment to the circuit model. This providing may include determining one or more respective cells that are candidates for adjustment by employing a sub-micron stress effect, and, for each candidate, replacing a candidate cell with a stressed cell, wherein a candidate cell and stressed cell perform a same logical function. Each stressed cell may include: a gate electrode, a first gate-cut shape disposed to cut the gate electrode, wherein the first gate-cut shape is disposed upon a row-boundary, a second gate-cut shape disposed upon the row-boundary, a gate-cut break disposed between the first gate-cut shape and the second gate-cut shape, an active region, and an active-cut shape disposed to cut the active region.Type: ApplicationFiled: July 12, 2016Publication date: November 23, 2017Inventors: Matthew BERZINS, Andrew Paul HOOVER