Patents by Inventor Paul A. Leveille
Paul A. Leveille has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10095590Abstract: A fault tolerant computer system having two virtual machines (VMs), each running on a separate host device, is connected over a network to one or more I/O devices. The system operates to monitor the health of one or more operational characteristics associated with each VM, and in the event that the health of both virtual machines dictates that one or the other of the VMs should be downgraded, but the system is not able to determine which VM should be downgraded and there is an imbalance in a monitored system operational characteristic, the system can defer downgrading one VM for a selected period of time during which the operational characteristic that is in imbalance is monitored. If the imbalance is resolved, the downgrade is cancelled, if an operational fault is confirmed prior to the expiration of the deferral period or if the deferral period expires, then one host is downgraded.Type: GrantFiled: May 5, 2016Date of Patent: October 9, 2018Inventors: Thomas D Bissett, Stephen J Wark, Paul A Leveille, James D McCollum, Angel L Pagan
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Patent number: 9924001Abstract: A method of allowing egress network frames to bypass the buffer requirement of a checkpoint system. In one embodiment, the method includes the steps of examining a frame, or its attributes, to determine if it is a “candidate frame” and if the frame is a candidate frame, allowing it to be released to the external network without an intervening checkpoint. In another embodiment, the candidate frame is one of a group comprising: any frame targeting a designated network interface; any frame of a designated protocol type; any frame sourced or destined from/to a designated address. In still another embodiment, the method includes the designation of scheduling follow-up checkpoints according to frame disposition to limit or reduce the effects of a fail-over (roll-back) disturbance.Type: GrantFiled: May 23, 2016Date of Patent: March 20, 2018Assignee: Stratus Technologies, Inc.Inventors: Stephen J Wark, Srinivasu Chinta, Paul A Leveille, Leslie R Sibley
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Patent number: 9760442Abstract: A method of delaying checkpointing in a virtual machine system. In one embodiment, the method includes the steps of examining a network frame to determine if it is a deferrable frame and if the frame is a deferrable frame, delaying a checkpoint associated with the frame. In another embodiment, the deferrable frame is one of a group comprising: an IP packet tagged with the ‘more fragments’ attribute; TCP data segments that lack the PSH flag and carry no flags other than ‘ACK’; and TCP segments that contain no data and carry only the ‘ACK’ flag; and any frame originating from or destined to a designated network address or port number. In still another embodiment, the method includes the step of concatenating the delays due to deferrable frames. In still yet another embodiment, the method further includes setting an upper limit to the amount of delay that can be generated.Type: GrantFiled: December 16, 2014Date of Patent: September 12, 2017Assignee: Stratus Technologies Bermuda Ltd.Inventors: Thomas D. Bissett, Paul A. Leveille, Srinivasu Chinta
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Patent number: 9652338Abstract: A method for determining a delay in a dynamic, event driven, checkpoint interval. In one embodiment, the method includes the steps of determining the number of network bits to be transferred; determining the target bit transfer rate; calculating the next cycle delay as the number of bits to be transferred divided by the target bit transfer rate. In another aspect, the invention relates to a method for delaying a checkpoint interval. In one embodiment, the method includes the steps of monitoring the transfer of a prior batch of network data and delaying a subsequent checkpoint until the transfer of a prior batch of network data has reached a certain predetermined level of completion. In another embodiment, the predetermined level of completion is 100%.Type: GrantFiled: December 16, 2014Date of Patent: May 16, 2017Assignee: Stratus Technologies Bermuda Ltd.Inventors: Thomas D. Bissett, Paul A. Leveille, Srinivasu Chinta
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Patent number: 9588844Abstract: In one aspect, the invention relates to a fault tolerant computing system. The system includes a primary virtual machine and a secondary virtual machine, wherein the primary and secondary virtual machines are in communication, wherein the primary virtual machine comprises a first checkpointing engine and a first network interface, wherein the secondary virtual machine comprises a second network interface, wherein the first checkpointing engine forwards a page of memory of the primary virtual machine to the second virtual machine such that the first checkpointing engine can checkpoint the page of memory without pausing the primary virtual machine.Type: GrantFiled: December 16, 2014Date of Patent: March 7, 2017Assignee: Stratus Technologies Bermuda Ltd.Inventors: Thomas D. Bissett, Paul A. Leveille
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Publication number: 20160373560Abstract: A method of allowing egress network frames to bypass the buffer requirement of a checkpoint system. In one embodiment, the method includes the steps of examining a frame, or its attributes, to determine if it is a “candidate frame” and if the frame is a candidate frame, allowing it to be released to the external network without an intervening checkpoint. In another embodiment, the candidate frame is one of a group comprising: any frame targeting a designated network interface; any frame of a designated protocol type; any frame sourced or destined from/to a designated address. In still another embodiment, the method includes the designation of scheduling follow-up checkpoints according to frame disposition to limit or reduce the effects of a fail-over (roll-back) disturbance.Type: ApplicationFiled: May 23, 2016Publication date: December 22, 2016Inventors: STEPHEN J. WARK, SRINIVASU CHINTA, PAUL A. LEVEILLE, LESLIE R. SIBLEY
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Publication number: 20160328302Abstract: A fault tolerant computer system having two virtual machines (VMs), each running on a separate host device, is connected over a network to one or more I/O devices. The system operates to monitor the health of one or more operational characteristics associated with each VM, and in the event that the health of both virtual machines dictates that one or the other of the VMs should be downgraded, but the system is not able to determine which VM should be downgraded and there is an imbalance in a monitored system operational characteristic, the system can defer downgrading one VM for a selected period of time during which the operational characteristic that is in imbalance is monitored. If the imbalance is resolved, the downgrade is cancelled, if an operational fault is confirmed prior to the expiration of the deferral period or if the deferral period expires, then one host is downgraded.Type: ApplicationFiled: May 5, 2016Publication date: November 10, 2016Inventors: THOMAS D. BISSETT, STEPHEN J. WARK, PAUL A. LEVEILLE, JAMES D. MCCOLLUM, ANGEL L. PAGAN
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Publication number: 20150205672Abstract: A method of delaying checkpointing in a virtual machine system. In one embodiment, the method includes the steps of examining a network frame to determine if it is a deferrable frame and if the frame is a deferrable frame, delaying a checkpoint associated with the frame. In another embodiment, the deferrable frame is one of a group comprising: an IP packet tagged with the ‘more fragments’ attribute; TCP data segments that lack the PSH flag and carry no flags other than ‘ACK’; and TCP segments that contain no data and carry only the ‘ACK’ flag; and any frame originating from or destined to a designated network address or port number. In still another embodiment, the method includes the step of concatenating the delays due to deferrable frames. In still yet another embodiment, the method further includes setting an upper limit to the amount of delay that can be generated.Type: ApplicationFiled: December 16, 2014Publication date: July 23, 2015Inventors: Thomas D. Bissett, Paul A. Leveille, Srinivasu Chinta
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Publication number: 20150205671Abstract: A method for determining a delay in a dynamic, event driven, checkpoint interval. In one embodiment, the method includes the steps of determining the number of network bits to be transferred; determining the target bit transfer rate; calculating the next cycle delay as the number of bits to be transferred divided by the target bit transfer rate. In another aspect, the invention relates to a method for delaying a checkpoint interval. In one embodiment, the method includes the steps of monitoring the transfer of a prior batch of network data and delaying a subsequent checkpoint until the transfer of a prior batch of network data has reached a certain predetermined level of completion. In another embodiment, the predetermined level of completion is 100%.Type: ApplicationFiled: December 16, 2014Publication date: July 23, 2015Inventors: Thomas D. Bissett, Paul A. Leveille, Srinivasu Chinta
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Publication number: 20150205673Abstract: In one aspect, the invention relates to a fault tolerant computing system. The system includes a primary virtual machine and a secondary virtual machine, wherein the primary and secondary virtual machines are in communication, wherein the primary virtual machine comprises a first checkpointing engine and a first network interface, wherein the secondary virtual machine comprises a second network interface, wherein the first checkpointing engine forwards a page of memory of the primary virtual machine to the second virtual machine such that the first checkpointing engine can checkpoint the page of memory without pausing the primary virtual machine.Type: ApplicationFiled: December 16, 2014Publication date: July 23, 2015Inventors: Thomas D. Bissett, Paul A. Leveille
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Patent number: 8812907Abstract: A computer system configured to provide fault tolerance includes a first host system and a second host system. The first host system is programmed to monitor a number of portions of memory of the first host system that have been modified by a guest running on the first host system and, upon determining that the number of portions exceeds a threshold level, determine that a checkpoint needs to be created. Upon determining that the checkpoint needs to be created, operation of the guest is paused and checkpoint data is generated. After generating the checkpoint data, operation of the guest is resumed while the checkpoint data is transmitted to the second host system.Type: GrantFiled: July 19, 2011Date of Patent: August 19, 2014Assignee: Marathon Technologies CorporationInventors: Thomas D. Bissett, Paul A. Leveille, Ted M. Lin, Jerry Melnick, Angel L. Pagan, Glenn A. Tremblay
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Patent number: 7877552Abstract: A symmetric multiprocessing fault-tolerant computer system controls memory access in a symmetric multiprocessing computer system. To do so, virtual page structures are created, where the virtual page structures reflect physical page access privileges to shared memory for processors in a symmetric multiprocessing computer system. Access to shared memory is controlled based on physical page access privileges reflected in the virtual paging structures to coordinate deterministic shared memory access between processors in the symmetric multiprocessing computer system. A symmetric multiprocessing fault-tolerant computer system may use duplication or continuous replay.Type: GrantFiled: May 23, 2006Date of Patent: January 25, 2011Assignee: Marathon Technologies CorporationInventors: Paul A. Leveille, Thomas D. Bissett, Stephen S. Corbin, Jerry Melnick, Glenn A. Tremblay, Satoshi Watanabe, Keiichi Koyama
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Publication number: 20090240916Abstract: A fault tolerant/fault resilient computer system includes a first coserver and a second coserver. The first coserver includes a first application environment (AE) processor and a first I/O subsystem processor on a first common motherboard. The second coserver includes a second AE processor and a second I/O subsystem processor on a second common motherboard.Type: ApplicationFiled: May 1, 2009Publication date: September 24, 2009Applicant: MARATHON TECHNOLOGIES CORPORATIONInventors: Glenn A. Tremblay, Paul A. Leveille, James D. McCollum, Thomas D. Bissett, J. Mark Pratt
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Patent number: 7373545Abstract: A fault-tolerant computer system includes at least two servers, each of which is configured to perform a first set of operations. Each of the two servers communicate with a computer that does not perform the first set of operations. In the event of a failure of a component of the system, determining which of the servers will continue to perform the first set of operations based on communication with the computer.Type: GrantFiled: May 8, 2006Date of Patent: May 13, 2008Assignee: Marathon Technologies CorporationInventors: Paul A. Leveille, Satoshi Watanabe, Keiichi Koyama
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Publication number: 20070214340Abstract: A symmetric multiprocessing fault-tolerant computer system controls memory access in a symmetric multiprocessing computer system. To do so, virtual page structures are created, where the virtual page structures reflect physical page access privileges to shared memory for processors in a symmetric multiprocessing computer system. Access to shared memory is controlled based on physical page access privileges reflected in the virtual paging structures to coordinate deterministic shared memory access between processors in the symmetric multiprocessing computer system. A symmetric multiprocessing fault-tolerant computer system may use duplication or continuous replay.Type: ApplicationFiled: May 23, 2006Publication date: September 13, 2007Applicant: Marathon Technologies CorporationInventors: Paul Leveille, Thomas Bissett, Stephen Corbin, Jerry Melnick, Glenn Tremblay, Satoshi Watanabe, Keiichi Koyama
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Publication number: 20060253727Abstract: A fault-tolerant computer system includes at least two servers, each of which is configured to perform a first set of operations. Each of the two servers communicate with a computer that does not perform the first set of operations. In the event of a failure of a component of the system, determining which of the servers will continue to perform the first set of operations based on communication with the computer.Type: ApplicationFiled: May 8, 2006Publication date: November 9, 2006Applicant: Marathon Technologies CorporationInventors: Paul Leveille, Satoshi Watanabe, Keiichi Koyama
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Publication number: 20050039074Abstract: A fault tolerant/fault resilient computer system includes a first coserver and a second coserver. The first coserver includes a first application environment (AE) processor and a first I/O subsystem processor on a first common motherboard. The second coserver includes a second AE processor and a second I/O subsystem processor on a second common motherboard. Each of the AE processors has a clock that operates asynchronously to clocks of the other AE processor, and the AE processors operate in instruction lockstep.Type: ApplicationFiled: July 8, 2004Publication date: February 17, 2005Inventors: Glenn Tremblay, Paul Leveille, James McCollum, Thomas Bissett, J. Pratt
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Patent number: 6728898Abstract: Producing a mirror copy using incremental-divergence is performed in a computer system in which write requests are each associated with a reference label. A mirror set may be restored to a state in which the data storage devices contain identical data by copying from the data storage device having “good” data only portions of data which have not been stored on the data storage device having divergent data. Incremental-divergence copying may be accomplished by keeping track of the changes made after a point in which the data storage devices are known to contain identical data.Type: GrantFiled: March 6, 2002Date of Patent: April 27, 2004Assignee: Marathon Technologies CorporationInventors: Glenn A. Tremblay, Paul A. Leveille, Charles H. Kaman, Gairy Grannum
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Publication number: 20030172316Abstract: Producing a mirror copy using incremental-divergence is performed in a computer system in which write requests are each associated with a reference label. A mirror set may be restored to a state in which the data storage devices contain identical data by copying from the data storage device having “good” data only portions of data which have not been stored on the data storage device having divergent data. Incremental-divergence copying may be accomplished by keeping track of the changes made after a point in which the data storage devices are known to contain identical data.Type: ApplicationFiled: March 6, 2002Publication date: September 11, 2003Inventors: Glenn A. Tremblay, Paul A. Leveille, Charles H. Kaman, Gairy Grannum
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Patent number: 6473869Abstract: A fault tolerant/fault resilient computer system includes at least two compute elements connected to at least one controller. Each compute element has clocks that operate asynchronously to clocks of the other compute elements. The compute elements operate in a first mode in which the compute elements each execute a first stream of instructions in emulated clock lockstep, and in a second mode in which the compute elements each execute a second stream of instructions in instruction lockstep. Each compute element may be a multi-processor compute element.Type: GrantFiled: August 10, 2001Date of Patent: October 29, 2002Assignee: Marathon Technologies CorporationInventors: Thomas D. Bissett, Paul A. Leveille, Erik Muench