Abstract: Embodiments of the present invention provide for the enhancement of transistors in a semiconductor structure using a strain layer. The structure comprises a patterned layer consisting of an excavated region and a pattern region, a strain layer located in the excavated region and on the pattern region, an active layer located above the strain layer, a field effect transistor formed in the active layer, and a handle layer located above the active layer. The field effect transistor comprises a source, a drain, and a channel. The channel lies completely within a lateral extent of the pattern region. The source and the drain each lie only partially within the lateral extent of the pattern region. The strain layer alters a carrier mobility of the channel. In some embodiments, the strain layer is introduced to the back side of a semiconductor-on-insulator structure.

Abstract: A semiconductor structure is formed with an active layer having an active device including a body region. The active device is formed by top side processing in and on a top side of a semiconductor on insulator wafer. A damaged region is formed within a portion of the body region by bottom side processing at a bottom side of the semiconductor on insulator wafer, the damaged region having a structure sufficient to prevent a kink effect and self-latching in operation of the active device.

Abstract: Embodiments of the present invention provide for the application of strain inducing layers to enhance the mobility of transistors formed on semiconductor-on-insulator (SOI) structures. In one embodiment, a method for fabricating an integrated circuit is disclosed. In a first step, active circuitry is formed in an active layer of a SOI wafer. In a second step, substrate material is removed from a substrate layer disposed on a back side of the SOI wafer. In a third step, insulator material is removed from the back side of the SOI wafer to form an excavated insulator region. In a fourth step, a strain inducing material is deposited on the excavated insulator region. The strain inducing material interacts with the pattern of excavated insulator such that a single layer provides both tensile and compressive stress to p-channel and n-channel transistors, respectively. In alternative embodiments, the entire substrate is removed before forming the strain inducing material.

Abstract: Embodiments of the present invention provide for the enhancement of transistors in a semiconductor structure using a strain layer. The structure comprises a patterned layer consisting of an excavated region and a pattern region, a strain layer located in the excavated region and on the pattern region, an active layer located above the strain layer, a field effect transistor formed in the active layer, and a handle layer located above the active layer. The field effect transistor comprises a source, a drain, and a channel. The channel lies completely within a lateral extent of the pattern region. The source and the drain each lie only partially within the lateral extent of the pattern region. The strain layer alters a carrier mobility of the channel. In some embodiments, the strain layer is introduced to the back side of a semiconductor-on-insulator structure.

Abstract: Various methods and devices that involve radio frequency (RF) switches with clamped bodies are provided. An exemplary RF switch with a clamped body comprises a channel that separates a source and a drain. The RF switch also comprises a clamp region that spans the channel, extends into the source and drain, and has a lower dopant concentration than both the source and drain. The RF switch also comprises a pair of matching silicide regions formed on either side of the channel and in contact with the clamp region. The clamp region forms a pair of Schottky diode barriers with the pair of matching silicide regions. The RF switch can operate in a plurality of operating modes. The pair of Schottky diode barriers provide a constant sink for accumulated charge in the clamped body that is independent of the operating mode in which the RF switch is operating.

Abstract: Various methods and devices that involve single transistor diode connected anti-fuse memory cells are disclosed. An exemplary memory cell comprises a thin gate insulator. The memory cell also comprises a bulk region of a first conductivity type in contact with a first side of the thin gate insulator. The memory cell also comprises a polysilicon gate electrode of the first conductivity type in contact with a second side of the thin gate insulator. The memory cell also comprises a source region of a second conductivity type in contact with the bulk region at a junction. The polysilicon gate electrode and the source region are operatively coupled to a programming voltage source that addresses the memory cell by blowing the thin gate insulator. The junction forms a diode for the memory cell. The bulk region can be in an active layer of a semiconductor on insulator structure.

Abstract: In one embodiment, an integrated circuit with a signal-processing region is disclosed. The integrated circuit comprises a silicon-on-insulator die singulated from a silicon-on-insulator wafer. The silicon on insulator die comprises an active layer, an insulator layer, a substrate, and a strengthening layer. The substrate consists of an excavated substrate region, and a support region, the support region is in contact with the insulator layer. The excavated region covers a majority of the signal-processing region of the integrated circuit.

Abstract: Embodiments of the present invention provide for the enhancement of transistors in a semiconductor structure using a strain layer. The structure comprises a patterned layer consisting of an excavated region and a pattern region, a strain layer located in the excavated region and on the pattern region, an active layer located above the strain layer, a field effect transistor formed in the active layer, and a handle layer located above the active layer. The field effect transistor comprises a source, a drain, and a channel. The channel lies completely within a lateral extent of the pattern region. The source and the drain each lie only partially within the lateral extent of the pattern region. The strain layer alters a carrier mobility of the channel. In some embodiments, the strain layer is introduced to the back side of a semiconductor-on-insulator structure.

Abstract: A semiconductor structure is formed with an active layer having an active device including a body region. The active device is formed by top side processing in and on a top side of a semiconductor on insulator wafer. A damaged region is formed within a portion of the body region by bottom side processing at a bottom side of the semiconductor on insulator wafer, the damaged region having a structure sufficient to prevent a kink effect and self-latching in operation of the active device.

Abstract: Various methods and devices that involve radio frequency (RF) switches with clamped bodies are provided. An exemplary RF switch with a clamped body comprises a channel that separates a source and a drain. The RF switch also comprises a clamp region that spans the channel, extends into the source and drain, and has a lower dopant concentration than both the source and drain. The RF switch also comprises a pair of matching silicide regions formed on either side of the channel and in contact with the clamp region. The clamp region forms a pair of Schottky diode barriers with the pair of matching silicide regions. The RF switch can operate in a plurality of operating modes. The pair of Schottky diode barriers provide a constant sink for accumulated charge in the clamped body that is independent of the operating mode in which the RF switch is operating.

Abstract: Various methods and devices that involve single transistor diode connected anti-fuse memory cells are disclosed. An exemplary memory cell comprises a thin gate insulator. The memory cell also comprises a bulk region of a first conductivity type in contact with a first side of the thin gate insulator. The memory cell also comprises a polysilicon gate electrode of the first conductivity type in contact with a second side of the thin gate insulator. The memory cell also comprises a source region of a second conductivity type in contact with the bulk region at a junction. The polysilicon gate electrode and the source region are operatively coupled to a programming voltage source that addresses the memory cell by blowing the thin gate insulator. The junction forms a diode for the memory cell. The bulk region can be in an active layer of a semiconductor on insulator structure.

Abstract: Various methods and devices that involve radio frequency (RF) switches with clamped bodies are provided. An exemplary RF switch with a clamped body comprises a channel that separates a source and a drain. The RF switch also comprises a clamp region that spans the channel, extends into the source and drain, and has a lower dopant concentration than both the source and drain. The RF switch also comprises a pair of matching silicide regions formed on either side of the channel and in contact with the clamp region. The clamp region forms a pair of Schottky diode barriers with the pair of matching silicide regions. The RF switch can operate in a plurality of operating modes. The pair of Schottky diode barriers provide a constant sink for accumulated charge in the clamped body that is independent of the operating mode in which the RF switch is operating.

Abstract: In one embodiment, an integrated circuit with a signal-processing region is disclosed. The integrated circuit comprises a silicon-on-insulator die singulated from a silicon-on-insulator wafer. The silicon on insulator die comprises an active layer, an insulator layer, a substrate, and a strengthening layer. The substrate consists of an excavated substrate region, and a support region, the support region is in contact with the insulator layer. The excavated region covers a majority of the signal-processing region of the integrated circuit.

Abstract: Embodiments of the present invention provide for the provisioning of efficient support to semiconductor-on-insulator (SOI) structures. Embodiments of the present invention may additionally provide for SOI structures with improved heat dissipation performance while preserving the beneficial electrical device characteristics that accompany SOI architectures. In one embodiment, an integrated circuit is disclosed. The integrated circuit comprises a silicon-on-insulator die from a silicon-on-insulator wafer. The silicon on insulator die comprises an active layer, an insulator layer, a substrate, and a strengthening layer. The substrate consists of an excavated substrate region, and a support region, the support region is in contact with the insulator layer. The support region and the strengthening layer are configured to act in combination to provide a majority of a required stabilizing force to the silicon-on-insulator die when it is singulated from the silicon-on-insulator wafer.

Abstract: Embodiments of the present invention provide for the dissipation of heat from semiconductor-on-insulator (SOI) structures. In one embodiment, a method for fabricating an integrated circuit is disclosed. In a first step, active circuitry is formed in an active layer of a SOI wafer. In a second step, substrate material is removed from a substrate layer disposed on a back side of the SOI wafer. In a third step, insulator material is removed from the back side of the SOI wafer to form an excavated insulator region. In a fourth step, a thermal dissipation layer is deposited on said excavated insulator region. The thermal dissipation layer is thermally conductive and electrically insulating.

Abstract: Embodiments of the present invention provide for the enhancement of transistors in a semiconductor structure using a strain layer. The structure comprises a patterned layer consisting of an excavated region and a pattern region, a strain layer located in the excavated region and on the pattern region, an active layer located above the strain layer, a field effect transistor formed in the active layer, and a handle layer located above the active layer. The field effect transistor comprises a source, a drain, and a channel. The channel lies completely within a lateral extent of the pattern region. The source and the drain each lie only partially within the lateral extent of the pattern region. The strain layer alters a carrier mobility of the channel. In some embodiments, the strain layer is introduced to the back side of a semiconductor-on-insulator structure.

Abstract: Embodiments of the present invention provide for the removal of excess carriers from the body of active devices in semiconductor-on-insulator (SOI) structures. In one embodiment, a method of fabricating an integrated circuit is disclosed. In one step, an active device is formed in an active layer of a semiconductor-on-insulator wafer. In another step, substrate material is removed from a substrate layer disposed on a back side of the SOI wafer. In another step, an insulator material is removed from a back side of the SOI wafer to form an excavated insulator region. In another step, a conductive layer is deposited on the excavated insulator region. Depositing the conductive layer puts it in physical contact with a body of an active device in a first portion of the excavated insulator region. The conductive layer then couples the body to a contact in a second detached portion of the excavated insulator region.

Abstract: Embodiments of the present invention provide for the removal of excess carriers from the body of active devices in semiconductor-on-insulator (SOI) structures. In one embodiment, a method of fabricating an integrated circuit is disclosed. In one step, an active device is formed in an active layer of a semiconductor-on-insulator wafer. In another step, substrate material is removed from a substrate layer disposed on a back side of the SOI wafer. In another step, an insulator material is removed from a back side of the SOI wafer to form an excavated insulator region. In another step, a conductive layer is deposited on the excavated insulator region. Depositing the conductive layer puts it in physical contact with a body of an active device in a first portion of the excavated insulator region. The conductive layer then couples the body to a contact in a second detached portion of the excavated insulator region.

Abstract: Embodiments of the present invention provide for the removal of excess carriers from the body of active devices in semiconductor-on-insulator (SOI) structures. In one embodiment, a method of fabricating an integrated circuit is disclosed. In one step, an active device is formed in an active layer of a semiconductor-on-insulator wafer. In another step, substrate material is removed from a substrate layer disposed on a back side of the SOI wafer. In another step, an insulator material is removed from a back side of the SOI wafer to form an excavated insulator region. In another step, a conductive layer is deposited on the excavated insulator region. Depositing the conductive layer puts it in physical contact with a body of an active device in a first portion of the excavated insulator region. The conductive layer then couples the body to a contact in a second detached portion of the excavated insulator region.

Abstract: Embodiments of the present invention provide for the dissipation of heat from semiconductor-on-insulator (SOI) structures. In one embodiment, a method for fabricating an integrated circuit is disclosed. In a first step, active circuitry is formed in an active layer of a SOI wafer. In a second step, substrate material is removed from a substrate layer disposed on a back side of the SOI wafer. In a third step, insulator material is removed from the back side of the SOI wafer to form an excavated insulator region. In a fourth step, a thermal dissipation layer is deposited on said excavated insulator region. The thermal dissipation layer is thermally conductive and electrically insulating.