Patents by Inventor Paul A. Packan
Paul A. Packan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240113118Abstract: Integrated circuit dies, apparatuses, systems, and techniques, are described herein related to low and ultra-low threshold voltage transistor cells. A first transistor cell includes separate semiconductor bodies contacted by separate gate electrodes having a dielectric material therebetween. A second transistor cell includes separate semiconductor bodies contacted by a shared gate electrode that couples to both semiconductor bodies. Transistors of the second transistor cell may be operated at a lower threshold voltage than those of the first transistor cell due to increased strain on the semiconductor bodies from the shared gate electrode.Type: ApplicationFiled: September 29, 2022Publication date: April 4, 2024Applicant: Intel CorporationInventors: Tao Chu, Minwoo Jang, Yanbin Luo, Paul A. Packan
-
Publication number: 20230317594Abstract: Embodiments disclosed herein include a semiconductor device. In an embodiment, the semiconductor device comprises a substrate and a transistor over the substrate. In an embodiment, the transistor comprises a source, a gate, and a drain. In an embodiment, the semiconductor device further comprises a first metal layer above the transistor, where the first metal layer comprises, a source metal coupled to the source, a drain metal coupled to the drain, and a gate metal coupled to the gate. In an embodiment, the source metal, the drain metal, and the gate metal are parallel conductive lines. In an embodiment, a backside via passes through the substrate, and a contact metal in the first metal layer is coupled to the backside via. In an embodiment, the contact metal is oriented orthogonal to the source metal.Type: ApplicationFiled: March 31, 2022Publication date: October 5, 2023Inventors: Tao CHU, Minwoo JANG, Aurelia WANG, Conor P. PULS, Lin HU, Jaladhi MEHTA, Brian GREENE, Chung-Hsun LIN, Walid M. HAFEZ, Paul PACKAN
-
Publication number: 20230253499Abstract: A method including forming an opening in a junction region of a fin on and extending from a substrate; introducing a doped semiconductor material in the opening; and thermal processing the doped semiconductor material. A method including forming a gate electrode on a fin extending from a substrate; forming openings in the fin adjacent opposite sides of the gate electrode; introducing a doped semiconductor material in the openings; and thermally processing the doped semiconductor material sufficient to induce the diffusion of a dopant in the doped semiconductor material. An apparatus including a gate electrode transversing a fin extending from a substrate; and semiconductor material filled openings in junction regions of the fin adjacent opposite sides of the gate electrode, wherein the semiconductor material comprises a dopant.Type: ApplicationFiled: April 13, 2023Publication date: August 10, 2023Inventors: Pratik A. PATEL, Mark Y. LIU, Jami A. WIEDEMER, Paul A. PACKAN
-
Patent number: 11664452Abstract: A method including forming an opening in a junction region of a fin on and extending from a substrate; introducing a doped semiconductor material in the opening; and thermal processing the doped semiconductor material. A method including forming a gate electrode on a fin extending from a substrate; forming openings in the fin adjacent opposite sides of the gate electrode; introducing a doped semiconductor material in the openings; and thermally processing the doped semiconductor material sufficient to induce the diffusion of a dopant in the doped semiconductor material. An apparatus including a gate electrode transversing a fin extending from a substrate; and semiconductor material filled openings in junction regions of the fin adjacent opposite sides of the gate electrode, wherein the semiconductor material comprises a dopant.Type: GrantFiled: October 30, 2020Date of Patent: May 30, 2023Assignee: Intel CorporationInventors: Pratik A. Patel, Mark Y. Liu, Jami A. Wiedemer, Paul A. Packan
-
Patent number: 11264517Abstract: A varactor is described that may be constructed in CMOS and has a high tuning range. In some embodiments, the varactor includes a well, a plurality of gates formed over the well and having a capacitive connection to the well, the gates comprising a first subset of the gates that are adjacent and consecutive and coupled to a positive pole of an excitation oscillation signal, and a second subset of the gates that are adjacent and consecutive and coupled to a negative pole of the excitation oscillation signal, and a plurality of source/drain terminals formed over the well and having an ohmic connection to the well, each coupled to a respective gate to receive a control voltage to control the capacitance of the varactor.Type: GrantFiled: December 24, 2014Date of Patent: March 1, 2022Assignee: Intel CorporationInventors: Mohammed El-Tanani, Paul Packan, Jami Wiedemer, Andrey Mezhiba, Yonping Fan
-
Publication number: 20210050448Abstract: A method including forming an opening in a junction region of a fin on and extending from a substrate; introducing a doped semiconductor material in the opening; and thermal processing the doped semiconductor material. A method including forming a gate electrode on a fin extending from a substrate; forming openings in the fin adjacent opposite sides of the gate electrode; introducing a doped semiconductor material in the openings; and thermally processing the doped semiconductor material sufficient to induce the diffusion of a dopant in the doped semiconductor material. An apparatus including a gate electrode transversing a fin extending from a substrate; and semiconductor material filled openings in junction regions of the fin adjacent opposite sides of the gate electrode, wherein the semiconductor material comprises a dopant.Type: ApplicationFiled: October 30, 2020Publication date: February 18, 2021Inventors: Pratik A. PATEL, Mark Y. LIU, Jami A. WIEDEMER, Paul A. PACKAN
-
Patent number: 10872977Abstract: A method including forming an opening in a junction region of a fin on and extending from a substrate; introducing a doped semiconductor material in the opening; and thermal processing the doped semiconductor material. A method including forming a gate electrode on a fin extending from a substrate; forming openings in the fin adjacent opposite sides of the gate electrode; introducing a doped semiconductor material in the openings; and thermally processing the doped semiconductor material sufficient to induce the diffusion of a dopant in the doped semiconductor material. An apparatus including a gate electrode transversing a fin extending from a substrate; and semiconductor material filled openings in junction regions of the fin adjacent opposite sides of the gate electrode, wherein the semiconductor material comprises a dopant.Type: GrantFiled: April 16, 2019Date of Patent: December 22, 2020Assignee: Intel CorporationInventors: Pratik A. Patel, Mark Y. Liu, Jami A. Wiedemer, Paul A. Packan
-
Publication number: 20190245088Abstract: A method including forming an opening in a junction region of a fin on and extending from a substrate; introducing a doped semiconductor material in the opening; and thermal processing the doped semiconductor material. A method including forming a gate electrode on a fin extending from a substrate; forming openings in the fin adjacent opposite sides of the gate electrode; introducing a doped semiconductor material in the openings; and thermally processing the doped semiconductor material sufficient to induce the diffusion of a dopant in the doped semiconductor material. An apparatus including a gate electrode transversing a fin extending from a substrate; and semiconductor material filled openings in junction regions of the fin adjacent opposite sides of the gate electrode, wherein the semiconductor material comprises a dopant.Type: ApplicationFiled: April 16, 2019Publication date: August 8, 2019Inventors: Pratik A. PATEL, Mark Y. LIU, Jami A. WIEDEMER, Paul A. PACKAN
-
Patent number: 10304956Abstract: A method including forming an opening in a junction region of a fin on and extending from a substrate; introducing a doped semiconductor material in the opening; and thermal processing the doped semiconductor material. A method including forming a gate electrode on a fin extending from a substrate; forming openings in the fin adjacent opposite sides of the gate electrode; introducing a doped semiconductor material in the openings; and thermally processing the doped semiconductor material sufficient to induce the diffusion of a dopant in the doped semiconductor material. An apparatus including a gate electrode transversing a fin extending from a substrate; and semiconductor material filled openings in junction regions of the fin adjacent opposite sides of the gate electrode, wherein the semiconductor material comprises a dopant.Type: GrantFiled: December 27, 2013Date of Patent: May 28, 2019Assignee: Intel CorporationInventors: Pratik A. Patel, Mark Y. Liu, Jami A. Wiedemer, Paul A. Packan
-
Publication number: 20170330977Abstract: A varactor is described that may be constructed in CMOS and has a high tuning range. In some embodiments, the varactor includes a well, a plurality of gates formed over the well and having a capacitive connection to the well, the gates comprising a first subset of the gates that are adjacent and consecutive and coupled to a positive pole of an excitation oscillation signal, and a second subset of the gates that are adjacent and consecutive and coupled to a negative pole of the excitation oscillation signal, and a plurality of source/drain terminals formed over the well and having an ohmic connection to the well, each coupled to a respective gate to receive a control voltage to control the capacitance of the varactor.Type: ApplicationFiled: December 24, 2014Publication date: November 16, 2017Inventors: MOHAMMED EL-TANANI, PAUL PACKAN, JAMI WIEDEMER, ANDREY MEZHIBA, YONPING FAN
-
Patent number: 9793373Abstract: Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics.Type: GrantFiled: March 16, 2017Date of Patent: October 17, 2017Assignee: Intel CorporationInventors: Anand S. Murthy, Robert S. Chau, Patrick Morrow, Chia-Hong Jan, Paul Packan
-
Publication number: 20170186855Abstract: Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics.Type: ApplicationFiled: March 16, 2017Publication date: June 29, 2017Inventors: Anand S. Murthy, Robert S. CHAU, Patrick MORROW, Chia-Hong JAN, Paul PACKAN
-
Patent number: 9640634Abstract: Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics.Type: GrantFiled: February 4, 2010Date of Patent: May 2, 2017Assignee: Intel CorporationInventors: Anand S. Murthy, Robert S. Chau, Patrick Morrow, Chia-Hong Jan, Paul Packan
-
Publication number: 20160380102Abstract: A method including forming an opening in a junction region of a fin on and extending from a substrate; introducing a doped semiconductor material in the opening; and thermal processing the doped semiconductor material. A method including forming a gate electrode on a fin extending from a substrate; forming openings in the fin adjacent opposite sides of the gate electrode; introducing a doped semiconductor material in the openings; and thermally processing the doped semiconductor material sufficient to induce the diffusion of a dopant in the doped semiconductor material. An apparatus including a gate electrode transversing a fin extending from a substrate; and semiconductor material filled openings in junction regions of the fin adjacent opposite sides of the gate electrode, wherein the semiconductor material comprises a dopant.Type: ApplicationFiled: December 27, 2013Publication date: December 29, 2016Inventors: Pratik A. PATEL, Mark Y. LIU, Jami A. WIEDEMER, Paul A. PACKAN
-
Patent number: 7888710Abstract: Complementary metal oxide semiconductor transistors are formed on a silicon substrate. The substrate has a {100} crystallographic orientation. The transistors are formed on the substrate so that current flows in the channels of the transistors are parallel to the <100> direction. Additionally, longitudinal tensile stress is applied to the channels.Type: GrantFiled: October 17, 2007Date of Patent: February 15, 2011Assignee: Intel CorporationInventors: Mark Armstrong, Gerhard Schrom, Sunit Tyagi, Paul A. Packan, Kelin J. Kuhn, Scott Thompson
-
Publication number: 20100133595Abstract: Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics.Type: ApplicationFiled: February 4, 2010Publication date: June 3, 2010Inventors: Anand S. Murthy, Robert S. Chau, Patrick Morrow, Chia-Hong Jan, Paul Packan
-
Patent number: 7682916Abstract: Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics.Type: GrantFiled: August 28, 2008Date of Patent: March 23, 2010Assignee: Intel CorporationInventors: Anand S. Murthy, Robert S. Chau, Patrick Morrow, Chia-Hong Jan, Paul Packan
-
Publication number: 20090323235Abstract: In some embodiments, semiconductor fabrication process charging protection is provided by coupling a first diode protection device to a high voltage node and coupling a second diode protection device to the first diode protection device at a second node. Other embodiments are described and claimed.Type: ApplicationFiled: June 30, 2008Publication date: December 31, 2009Inventors: Sangwoo Pae, Jeff Jones, Greg Taylor, Paul Packan, Bruce Woolery, Jeff Hicks
-
Publication number: 20090011565Abstract: Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics.Type: ApplicationFiled: August 28, 2008Publication date: January 8, 2009Inventors: Anand S. Murthy, Robert S. Chau, Patrick Morrow, Chia-Hong Jan, Paul Packan
-
Patent number: 7436035Abstract: Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics.Type: GrantFiled: August 12, 2004Date of Patent: October 14, 2008Assignee: Intel CorporationInventors: Anand S. Murthy, Robert S. Chau, Patrick Morrow, Chia-Hong Jan, Paul Packan