Abstract: Circuits and methods are provided for aligning data read from a memory with an output clock signal when the memory is operated at very high clock frequencies. To align data and clock signals when needed, delay is added to the output clock signal during the read operation. This alignment allows various timing specifications to be met when they would otherwise be violated, therefore improving data integrity in the system.

Abstract: The illustrated embodiments relate to a control circuit that is adapted to use a latency signal to generate an output signal. The latency is adapted to be used to create a control signal that is dependent on the latency signal. The control signal is adapted to be used to select from among multiple input sources. The selected input source is adapted to be used to create an output signal.

Abstract: A delay circuit delays an input signal to produce an output signal. The input and output signals have a delay which is based on a signal relationship between the input signal and a reference signal. The delay circuit includes configurable devices to vary the reference signal to adjust the delay between the input and output signals.

Abstract: A delay locked loop includes a forward path for receiving an input signal to provide an output signal, a feedback path for providing a feedback signal based on the output signal, and a controller responsive to a timing relationship between the feedback signal and the input signal for adjusting a timing of the output signal. The feedback path includes an adjustable delay circuit for adjusting a timing of the feedback signal.

Abstract: The illustrated embodiments relate to a control circuit that is adapted to use a latency signal to generate an output signal. The latency is adapted to be used to create a control signal that is dependent on the latency signal. The control signal is adapted to be used to select from among multiple input sources. The selected input source is adapted to be used to create an output signal.

Abstract: The illustrated embodiments relate to a control circuit that uses a latency signal to generate an output signal. The latency is used to create a control signal that is dependent on the latency signal. The control signal is used to select from among multiple input sources. The selected input source is used to create an output signal.

Abstract: The illustrated embodiments relate to a control circuit that uses a latency signal to generate an output signal. The latency is used to create a control signal that is dependent on the latency signal. The control signal is used to select from among multiple input sources. The selected input source is used to create an output signal.

Abstract: A delay locked loop includes a delay line for delaying an input signal generated from an external signal. A delay controller controls the delay line to keep the external and internal signals synchronized. The delay locked loop also includes cycle control circuitry for controlling the cycle time of the signal entering the delay and the cycle time of the signal exiting the delay line.

Abstract: A delay circuit that delays an input signal to produce an output signal. The input signal and output signals has a delay which is based on a signal relationship between the input signal and a reference signal. The delay circuit includes configurable devices to vary the reference signal to adjust the delay between the input and output signals.

Abstract: A method and apparatus to dynamically set the insertion point of a delay line control shift register based on the current cycle time. A string of delay elements equivalent to the delay elements in a delay lock loop (DLL) are laid out in the opposite direction compared to the DLL delay elements. Both strings of delay elements receive a synchronous input signal such as an external clock signal. The output clock signal of the DLL is phase-shifted relative to the external clock signal such that data removed from a device such as a synchronous dynamic random access memory (SDRAM) device is synchronous with the external clock signal. When a DLL reset command is issued, the information from the string of delay elements is captured and used to set the insertion point of the DLL to the locked or phase-equal point. This allows the DLL to quickly lock on any frequency upon reset of the DLL.

Abstract: A method of forcing a data strobe signal of a memory device on without requiring a read command to be issued is provided. The data strobe signal is controlled by a delay locked loop (DLL). During a normal mode of operation, the DLL turns on the data strobe signal only after a read command is issued to the memory device. The data strobe signal is used as reference signal to track a data signal output from memory cells of the memory device during a read operation. By forcing the data strobe signal on without issuing a read command during a test mode, the characteristics of the DLL in response to other commands can be observed.