Abstract: A pull-model system and method provides display data over a network to a plurality of display devices having the same or different video format requirements. Utilization of image memory bandwidth is balanced between the plurality of display devices. Based on image memory bandwidth requirements for the plurality of display devices, a bandwidth allocation table is generated to indicate a servicing priority for the display devices. A plurality of requests for pixel data are received and stored in a request buffer. The requests are then serviced in an order indicated by the bandwidth allocation table.

Abstract: A high-speed, 3-stage, pipelined architecture floating point accumulator circuit having a pre-normalization feedback loop for accumulated numbers to increase processing speed.

Abstract: A multifunction arithmetic logic circuit having comparison and numeric conversion circuitry, particularly adapted for use in graphics processing. The inventive architecture comprises a modular arithmetic logic unit in a pipelined architecture circuit. Functions performed are conversion of floating point numbers to fixed point numbers, and vise versa, arithmetic and logical operations, and numeric comparison operations. A visibility logic subcircuit is included for rapidly tracking numeric comparisons to indicate whether a graphics object is to be considered visible, partially visible, or invisible.