Abstract: Regions of frame buffer memory are selectively read by a computer graphics system in a bandwidth efficient manor. Attribute data for each pixel is stored in the frame buffer memory array. This attribute data, when decoded, selects which regions of frame buffer memory are required for display of each pixel. Pixels are grouped as tiles. Before each tile is displayed, attribute data is read for that tile, then decoded, and the frame buffer memory is accessed only for those regions that are needed to display the current tile of pixels.

Abstract: Disclosed herein is an improvement to a reservation booking website for rental vehicle reservations wherein the functionality of managing customer profiles/accounts is expanded upon to provide customers with greater control over the profile data stored in their associated personalized accounts/profiles, particularly in connection with the “favorite” or “preferred” branch locations for rental vehicle reservations that are stored in the customer profiles/accounts. Also disclosed herein is an improvement to a reservation booking website wherein customers who plan to travel via general aviation (GA) are provided with a GA reservation creation path that is responsive to their GA travel needs. Also disclosed herein is an improvement to a reservation booking website for rental vehicle reservations wherein customers are provided with a streamlined ability to log into their customer profiles/accounts.

Abstract: A method of processing a reservation transaction between a customer and reservation-booking entity via a computer network inter-connecting a customer computer with an automated reservation transaction processor, the reservation transaction requiring submission of at least three different types of reservation data from the customer for successful completion thereof, each reservation data type having one of a plurality of different values, wherein each reservation data type value is dependent upon other reservation data type values, the method including presenting an initial page for data value entry for a plurality of reservation data types, accepting for partial data entry data values for less than all of said reservation data types, and determining, on the basis of the interdependence of the different data values for the different reservation data types, a list of acceptable data values for any un-entered reservation data types.

Abstract: A combination error detector to detect errors in an InfiniBand packet. The detector includes registers that stores fields of an InfiniBand packet as the packet is being received and comparison logic that, as the fields are stored in the registers, compares the fields with check values and when an error is detected sets a flag corresponding to the error. After the packet has been completely received and all checks have been complete, all of the error flags are prioritized in accordance with the InfiniBand Architecture Specification.

Abstract: An infiniband architecture switch, includes an error checker having a plurality of inputs and an output signal bus, the error checker configured to identify at least one data-packet error condition responsive to signals at the plurality of inputs, and an error recorder communicatively coupled to the error checker via the output signal bus wherein the error recorder contains a representation of data-packet errors. A method for identifying data-packet errors includes, monitoring for the occurrence of at least one data-packet error condition in a port of an infiniband architecture switch, encoding a representation of the at least one data-packet error condition, and forwarding the representation to an error recorder.

Abstract: An infiniband architecture switch, includes a plurality of ports each configured to receive switch parameters, identify at least one data-packet error condition responsive to the switch parameters, generate a trap-initialization signal when the at least one data-packet error condition matches a trap-error condition, and a switch manager configured to receive the trap-initialization signal. A method for generating a switch manager control signal includes identifying at least one data-packet error condition in an infiniband architecture switch, determining when the at least one data-packet error condition matches a trap-error condition, generating a trap-initialization signal responsive to the trap-error condition, and forwarding the trap-initialization signal to a switch manager.

Abstract: A method and structure for the handling and discarding of packets in a packet data network. The method includes a packet data network receiving one or more packets from one or more remote locations and initiating a transfer of a packet of the one or more packets to a remote destination. The remote destination is operable to act as a destination port of a switch. The transfer of the packet is initiated while the packet of the one or more packets is being received, and the packet validity is also checked while the transfer of the packet is initiated. If the packet is invalid, the transfer of the packet of the one or more packets to the remote destination is canceled. Determining packet validity includes inspection of a packet header. The structure has a receive link determining packet validity and passing this error signal to a packet processor. The packet processor has a packet transfer request generator, a packet checker, packet reader, packet memory and tag memory.

Abstract: In general, a system and method for providing data packet flow control is disclosed. Generally, a switch is provided that contains a series of ports, an arbiter and a hub. The arbiter determines an outgoing port, wherein the outgoing port is one port for the series of ports, for transmission of a data packet received by the switch, determines whether the outgoing port is available to receive the received data packet, and regulates transmission of the received data packet to a destination end node. The hub provides a point-to-point connection between any two of the series of ports and the arbiter.

Abstract: A method of processing a reservation transaction between a customer and reservation-booking entity via a computer network inter-connecting a customer computer with an automated reservation transaction processor, the reservation transaction requiring submission of at least three different types of reservation data from the customer for successful completion thereof, each reservation data type having one of a plurality of different values, wherein each reservation data type value is dependent upon other reservation data type values, the method including presenting an initial page for data value entry for a plurality of reservation data types, accepting for partial data entry data values for less than all of said reservation data types, and determining, on the basis of the interdependence of the different data values for the different reservation data types, a list of acceptable data values for any un-entered reservation data types.

Abstract: Internal memory elements of vendor-specific network devices are made available using standardized network protocol packets. In accordance with the invention, reserved values of an attribute identifier field may be mapped to implementation-specific nodes within a particular manufacturer's network device, while a set of reserved attribute modifier values may be mapped to implementation-specific memory elements within the node specified by the value of the attribute identifier. Access to implementation-specific device internals is therefore made possible using the standard network protocol.

Abstract: A switch for use with an InfiniBand network. The switch includes a crossbar that redirects packet based data based on a forwarding table. At least one port that receives data from a network and selectively transfers that data to the crossbar at 1×, 4×, and 12× speeds. A state machine that controls the changing of the speed of operation of the port.

Abstract: A combination error detector to detect errors in an InfiniBand packet. The detector includes registers that stores fields of an InfiniBand packet as the packet is being received and comparison logic that, as the fields are stored in the registers, compares the fields with check values and when an error is detected sets a flag corresponding to the error. After the packet has been completely received and all checks have been complete, all of the error flags are prioritized in accordance with the InfiniBand Architecture Specification.

Abstract: A switch for use with an InfiniBand network. The switch includes a crossbar that redirects packet-based data based on a forwarding table. At least one port that receives data from a network and selectively transfers that data to the crossbar using a variable number of virtual lanes. A state machine controls the changing of the number of virtual lanes.

Abstract: An early detection system is presented in which flow control logic is used to continually assess the capacity of a buffer memory. The flow control logic maintains an update of the buffer memory based on the buffer memories ability to store information associated with one of eight virtual lanes. As a result of the assessment, the flow control logic is capable of generating an early full detect signal. The early full detect signal denotes the capability of the buffer memory to hold packet information in a specific virtual lane. Packet checker logic receives the early full detect signal and assesses the first byte (e.g. first three bits) of a packet header, to determine whether the buffer memory can store information. If the packet passes the early detect test a second test is performed to determine if the buffer memory has enough space to store the packet. Should the buffer memory be unable to store information, the packet is discarded.

Abstract: Regions of frame buffer memory are selectively read by a computer graphics system in a bandwidth efficient manor. Attribute data for each pixel is stored in the frame buffer memory array. This attribute data, when decoded, selects which regions of frame buffer memory are required for display of each pixel. Pixels are grouped as tiles. Before each tile is displayed, attribute data is read for that tile, then decoded, and the frame buffer memory is accessed only for those regions that are needed to display the current tile of pixels.

Abstract: A computer graphics system includes an apparatus for fog blending colors to be displayed on a graphics display of the computer graphics system. The computer graphics system includes a rendering parameter calculation unit responsive to data of a primitive, that determines a cooked exponent value and a color value for at least one pixel of the primitive. In addition, the system includes a fog unit responsive to the cooked exponent value for each pixel of the primitive, that determines a fog blending factor for each pixel of the primitive, wherein the fog blending factor is one of an exponential fog blending factor and an exponential-squared fog blending factor.

Abstract: The invention provides for a system and method for minimizing space requirements and increasing speed in a geometry accelerator for a computer graphics system. In architecture, the system is implemented as follows. The geometry accelerator includes a plurality of processing elements (e.g., an arithmetic logic unit, a multiplier, a divider, a compare mechanism, a clamp mechanism, etc.) and a plurality of control units (e.g., a transform mechanism, a decomposition mechanism, a clip mechanism, a bow-tie mechanism, a light mechanism, a classify mechanism, a plane equation mechanism, a fog mechanism, etc.) that utilize the processing elements for performing data manipulations upon image data. In accordance with the invention, the control units are implemented in a read-only memory (ROM) via microcode. A next address field is associated with each of the microcode instructions and defines a location in the ROM of a next instruction to be executed.

Abstract: The invention provides for a system and method for minimizing space requirements and increasing speed in a geometry accelerator for a computer graphics system by providing a branch central intelligence mechanism. Architecturally, the geometry accelerator includes a plurality of processing elements (e.g., an arithmetic logic unit, a multiplier, a divider, a compare mechanism, a clamp mechanism, etc.) and a plurality of control units (e.g., a transform mechanism, a decomposition mechanism, a clip mechanism, a bow-tie mechanism, a light mechanism, a classify mechanism, a plane equation mechanism, a fog mechanism, etc.) that utilize the processing elements for performing data manipulations upon image data. In accordance with the invention, the control units are implemented in a read-only memory (ROM) via microcode. A next address field is associated with each of the microcode instructions and defines a location in the ROM of a next instruction to be executed.

Abstract: A thermal management device for an enclosure, the enclosure disposed in an environment exposed to ambient air and having an interior area for housing heat generating electronic components includes a heat exchanger having an evaporator portion and a condenser portion, the evaporator portion is adapted for mounting within the enclosure interior area adjacent to the heat generating electronic components. The condenser portion is exposed to the ambient air for removal of heat from the enclosure interior area generated by the electronic components adjacent to the heat exchanger evaporator portion. The device is incorporated in a system which includes an air duct disposed within the enclosure interior area. The duct includes an air inlet port and air outlet port. The ports communicate with the ambient air to thereby create an airflow path through the air duct from the inlet port to the outlet port.