Patents by Inventor Paul Accisano
Paul Accisano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11877522Abstract: Systems and methods for determining critical timing paths in a superconducting circuit design including Josephson junctions are provided. An example method includes providing timing information concerning a plurality of source terminals of at least one logic gate coupled with a first sink terminal of the at least one logic gate. The method further includes using a processor, determining whether, in view of the timing information, the first sink terminal is reachable by a single flux quantum (SFQ) pulse within a predetermined range of arrival time based on an assigned first phase to the at least one logic gate.Type: GrantFiled: June 3, 2022Date of Patent: January 16, 2024Assignee: Microsoft Technology Licensing, LLCInventors: Janet L Schneider, Paul Accisano, Mark G. Kupferschmidt, Kenneth Reneris
-
Patent number: 11836434Abstract: A system and method for the automatic placement of superconducting devices determines an arrangement of a series of Josephson junctions between a start point and an end point of an inductive wiring run on a superconducting circuit layout having a plurality of discrete Josephson junction placement sites by determining costs of placing each Josephson junction of the series of Josephson junctions at the plurality of discrete Josephson junction placement sites between the start point and the end point of the inductive wiring run based at least on a comparison of a target inductance value to inductances of wires connecting to the Josephson junction and selecting sites from the plurality of discrete Josephson junction placement sites to place each Josephson junction corresponding to the arrangement of the series of Josephson junctions with the least determined cost for the inductive wiring run.Type: GrantFiled: April 20, 2021Date of Patent: December 5, 2023Assignee: Microsoft Technology Licensing, LLCInventors: Paul Accisano, Srinivas Raghu Gatta, Kenneth Reneris, Michael Goulding
-
Patent number: 11620430Abstract: A system and method for the automatic placement of superconducting devices determines an arrangement of a series of Josephson junctions between a start point and an end point of an inductive wiring run on a superconducting circuit layout having a plurality of discrete Josephson junction placement sites by determining costs of placing each Josephson junction of the series of Josephson junctions at the plurality of discrete Josephson junction placement sites between the start point and the end point of the inductive wiring run based at least on a comparison of a target inductance value to inductances of wires connecting to the Josephson junction and selecting sites from the plurality of discrete Josephson junction placement sites to place each Josephson junction corresponding to the arrangement of the series of Josephson junctions with the least determined cost for the inductive wiring run.Type: GrantFiled: April 20, 2021Date of Patent: April 4, 2023Assignee: Microsoft Technology Licensing, LLCInventors: Paul Accisano, Srinivas Raghu Gatta, Kenneth Reneris, Michael Goulding
-
Patent number: 11544438Abstract: A system and method for placing Josephson junction splitters on a superconducting circuit layout receives a specification of locations to be connected by a number of Josephson transmission lines. The system determines, based on the specification, a topology specifying connections between the locations, the topology including a plurality of 1-to-2 Josephson junction splitter nodes. The system determines splitter node locations based at least on ranges determined from distances between adjacent range endpoints of a previous level of the topology, and the system places each of the 1-to-2 Josephson junction splitter nodes at the determined splitter node locations.Type: GrantFiled: April 27, 2021Date of Patent: January 3, 2023Assignee: Microsoft Technology Licensing, LLCInventors: Paul Accisano, Kenneth Reneris
-
Publication number: 20220343049Abstract: A system and method for placing Josephson junction splitters on a superconducting circuit layout receives a specification of locations to be connected by a number of Josephson transmission lines. The system determines, based on the specification, a topology specifying connections between the locations, the topology including a plurality of 1-to-2 Josephson junction splitter nodes. The system determines splitter node locations based at least on ranges determined from distances between adjacent range endpoints of a previous level of the topology, and the system places each of the 1-to-2 Josephson junction splitter nodes at the determined splitter node locations.Type: ApplicationFiled: April 27, 2021Publication date: October 27, 2022Inventors: Paul ACCISANO, Kenneth RENERIS
-
Publication number: 20220335198Abstract: A system and method for the automatic placement of superconducting devices determines an arrangement of a series of Josephson junctions between a start point and an end point of an inductive wiring run on a superconducting circuit layout having a plurality of discrete Josephson junction placement sites by determining costs of placing each Josephson junction of the series of Josephson junctions at the plurality of discrete Josephson junction placement sites between the start point and the end point of the inductive wiring run based at least on a comparison of a target inductance value to inductances of wires connecting to the Josephson junction and selecting sites from the plurality of discrete Josephson junction placement sites to place each Josephson junction corresponding to the arrangement of the series of Josephson junctions with the least determined cost for the inductive wiring run.Type: ApplicationFiled: April 20, 2021Publication date: October 20, 2022Inventors: Paul ACCISANO, Srinivas Raghu GATTA, Kenneth RENERIS, Michael GOULDING
-
Publication number: 20220328748Abstract: Systems and methods for determining critical timing paths in a superconducting circuit design including Josephson junctions are provided. An example method includes providing timing information concerning a plurality of source terminals of at least one logic gate coupled with a first sink terminal of the at least one logic gate. The method further includes using a processor, determining whether, in view of the timing information, the first sink terminal is reachable by a single flux quantum (SFQ) pulse within a predetermined range of arrival time based on an assigned first phase to the at least one logic gate.Type: ApplicationFiled: June 3, 2022Publication date: October 13, 2022Inventors: Janet L. SCHNEIDER, Paul ACCISANO, Mark G. KUPFERSCHMIDT, Kenneth RENERIS
-
Patent number: 11380835Abstract: Systems and methods for determining critical timing paths in a superconducting circuit design including Josephson junctions are provided. An example method includes providing timing information concerning a plurality of source terminals of at least one logic gate coupled with a first sink terminal of the at least one logic gate. The method further includes using a processor, determining whether, in view of the timing information, the first sink terminal is reachable by a single flux quantum (SFQ) pulse within a predetermined range of arrival time based on an assigned first phase to the at least one logic gate.Type: GrantFiled: July 22, 2019Date of Patent: July 5, 2022Assignee: Microsoft Technology Licensing, LLCInventors: Janet L. Schneider, Paul Accisano, Mark G. Kupferschmidt, Kenneth Reneris
-
Publication number: 20220180038Abstract: Systems and methods for determining critical timing paths in a superconducting circuit design including Josephson junctions are provided. An example method includes providing timing information concerning a plurality of source terminals of at least one logic gate coupled with a first sink terminal of the at least one logic gate. The method further includes using a processor, determining whether, in view of the timing information, the first sink terminal is reachable by a single flux quantum (SFQ) pulse within a predetermined range of arrival time based on an assigned first phase to the at least one logic gate.Type: ApplicationFiled: July 22, 2019Publication date: June 9, 2022Inventors: Janet L. Schneider, Paul Accisano, Mark G. Kupferschmidt, Kenneth Reneris
-
Patent number: 10769344Abstract: Systems and methods for determining timing paths and reconciling topology in a superconducting circuit design are provided. The design may include a first timing path having a first set of timing pins associated with a first timing constraint group including a first timing endpoint and a second timing endpoint. An example method includes processing the first timing constraint group to assign a first legal start time to the first timing endpoint and a second legal start time to the second timing endpoint. The method further includes inserting a first shadow element representing a first physically connected component on the timing path, where the first shadow element precedes the first timing endpoint or follows the second timing endpoint. The method further includes addressing any changes to the first legal start time or the second legal start time caused by an insertion of the first shadow element on the timing path.Type: GrantFiled: July 22, 2019Date of Patent: September 8, 2020Assignee: Microsoft Technology Licensing, LLCInventors: Janet L. Schneider, Paul Accisano, Mark G. Kupferschmidt, Kenneth Reneris