Patents by Inventor Paul Ackmann
Paul Ackmann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11651992Abstract: The present disclosure relates to semiconductor structures and, more particularly, to gap fill void and connection structures and methods of manufacture. The structure includes: a gate structure comprising source and drain regions; a gate contact in direct contact and overlapping the gate structure; and source and drain contacts directly connecting to the source and drain regions, respectively.Type: GrantFiled: January 11, 2021Date of Patent: May 16, 2023Assignee: GLOBALFOUNDRIES U.S. Inc.Inventors: Haigou Huang, Yuping Ren, Paul Ackmann, Guoxiang Ning
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Publication number: 20210134658Abstract: The present disclosure relates to semiconductor structures and, more particularly, to gap fill void and connection structures and methods of manufacture. The structure includes: a gate structure comprising source and drain regions; a gate contact in direct contact and overlapping the gate structure; and source and drain contacts directly connecting to the source and drain regions, respectively.Type: ApplicationFiled: January 11, 2021Publication date: May 6, 2021Inventors: Haigou HUANG, Yuping REN, Paul ACKMANN, Guoxiang NING
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Patent number: 10923388Abstract: The present disclosure relates to semiconductor structures and, more particularly, to gap fill void and connection structures and methods of manufacture. The structure includes: a gate structure comprising source and drain regions; a gate contact in direct contact and overlapping the gate structure; and source and drain contacts directly connecting to the source and drain regions, respectively.Type: GrantFiled: January 18, 2019Date of Patent: February 16, 2021Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Haigou Huang, Yuping Ren, Paul Ackmann, Guoxiang Ning
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Publication number: 20200235002Abstract: The present disclosure relates to semiconductor structures and, more particularly, to gap fill void and connection structures and methods of manufacture. The structure includes: a gate structure comprising source and drain regions; a gate contact in direct contact and overlapping the gate structure; and source and drain contacts directly connecting to the source and drain regions, respectively.Type: ApplicationFiled: January 18, 2019Publication date: July 23, 2020Inventors: Haigou HUANG, Yuping REN, Paul ACKMANN, Guoxiang NING
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Patent number: 10002827Abstract: Methods for identification and partial re-routing of selected areas (e.g., including critical areas) in a layout of an IC design and the resulting device are disclosed. Embodiments include comparing design data of an IC device against criteria of manufacturing processes to manufacture the IC device; identifying in the design data a layout area based, at least in part, on proximity of metal segments, interconnecting segments, or a combination thereof in the layout area; performing partial re-routing in the layout area to substantially meet the criteria, wherein at least one interconnecting element is shifted or extended; and integrating the partial re-routing into the design data for use in the manufacturing processes.Type: GrantFiled: March 14, 2017Date of Patent: June 19, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Guoxiang Ning, Yuping Ren, Chin Teong Lim, Xusheng Wu, Paul Ackmann
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Patent number: 9864831Abstract: A metrology pattern layout for a circuit structure is provided, the metrology pattern layout including a plurality of quadrants, in which quadrants a first wafer measurement pattern, a second wafer measurement pattern, a reticle registration pattern, and a reticle measurement pattern may be arranged to facilitate correlation of reticle metrology data with wafer metrology data. The reticle registration pattern may further include one or more outermost structural elements designed to protect other structural elements within the reticle measurement pattern from being modified in an optical proximity correction process. A method of optical proximity correction process is provided, in which a reticle measurement pattern may be obtained and classified to add or modify a rule set of the optical proximity correction process.Type: GrantFiled: March 16, 2016Date of Patent: January 9, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: Guoxiang Ning, Guido Ueberreiter, Lloyd C. Litt, Paul Ackmann
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Patent number: 9817940Abstract: A method includes receiving a layout of an integrated circuit that includes a plurality of layers, one of the layers is selected and one or more tile number values are provided. A die area of the integrated circuit is partitioned into a plurality of tiles on the basis of the tile number values. It is determined, on the basis of the layout, if a portion of the selected one of the layers in the tile has an available space for inclusion of a test cell or a dummy cell, and a label indicative of a result is assigned to the tile. It is determined, on the basis of the labels assigned, if one or more space availability criteria are fulfilled and, if fulfilled, the labels are used for placing at least one of one or more test cells and one or more dummy cells in the layout.Type: GrantFiled: May 3, 2017Date of Patent: November 14, 2017Assignee: GLOBALFOUNDRIES Inc.Inventors: Guido Ueberreiter, Paul Ackmann, Guoxiang Ning, Jui-Hsuan Feng, Chin Teong Lim
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Patent number: 9798238Abstract: Methods for reducing reticle transmission differences and for optimizing layer placement for overlay in MTRs and CTRs are disclosed. Embodiments include providing a reticle having a prime area and a frame area surrounding the prime area; determining RT differences across the prime area; and providing RT adjustment structures on the reticle to decrease the RT differences. Other embodiments include grouping multiple layers of a semiconductor production flow, the layers for each group having an RT difference less than a predetermined value; and placing the layers on plural ordered reticles of a reticle set, each reticle having multiple image fields, by selecting, for each reticle, layers from a single group and optimizing placement of the layers for overlay. Other embodiments include selectively rotating image fields on a reticle having multiple image fields to improve overlay, or optimizing placement of DDLs on CTRs by placing each design orientation on a different reticle.Type: GrantFiled: February 26, 2016Date of Patent: October 24, 2017Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Guo Xiang Ning, Arthur Hotzel, Paul Ackmann, Soon Yoeng Tan
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Patent number: 9791772Abstract: Reticle and methods for forming a device or reticle are presented. A reticle is provided with a device pattern and a first monitoring pattern. The first monitoring pattern includes a plurality of first test cells having a first test cell area and a first test pattern. The first test cells have different first pitch ratios to an anchor pitch and the first test pattern fills the first test cell area of a first test cell. A wafer with a resist layer is exposed with a lithographic system using the reticle. The resist is developed to form a patterned resist layer on the wafer and the wafer is processed using the patterned resist layer.Type: GrantFiled: November 19, 2013Date of Patent: October 17, 2017Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Guoxiang Ning, Paul Ackmann, Byoung Il Choi
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Publication number: 20170235866Abstract: A method includes receiving a layout of an integrated circuit that includes a plurality of layers, one of the layers is selected and one or more tile number values are provided. A die area of the integrated circuit is partitioned into a plurality of tiles on the basis of the tile number values. It is determined, on the basis of the layout, if a portion of the selected one of the layers in the tile has an available space for inclusion of a test cell or a dummy cell, and a label indicative of a result is assigned to the tile. It is determined, on the basis of the labels assigned, if one or more space availability criteria are fulfilled and, if fulfilled, the labels are used for placing at least one of one or more test cells and one or more dummy cells in the layout.Type: ApplicationFiled: May 3, 2017Publication date: August 17, 2017Inventors: Guido Ueberreiter, Paul Ackmann, Guoxiang Ning, Jui-Hsuan Feng, Chin Teong Lim
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Publication number: 20170186687Abstract: Methods for identification and partial re-routing of selected areas (e.g., including critical areas) in a layout of an IC design and the resulting device are disclosed. Embodiments include comparing design data of an IC device against criteria of manufacturing processes to manufacture the IC device; identifying in the design data a layout area based, at least in part, on proximity of metal segments, interconnecting segments, or a combination thereof in the layout area; performing partial re-routing in the layout area to substantially meet the criteria, wherein at least one interconnecting element is shifted or extended; and integrating the partial re-routing into the design data for use in the manufacturing processes.Type: ApplicationFiled: March 14, 2017Publication date: June 29, 2017Inventors: Guoxiang NING, Yuping REN, Chin Teong LIM, Xusheng WU, Paul ACKMANN
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Patent number: 9672313Abstract: Methods for identification and partial re-routing of selected areas (e.g., including critical areas) in a layout of an IC design and the resulting device are disclosed. Embodiments include comparing design data of an IC device against criteria of manufacturing processes to manufacture the IC device; identifying in the design data a layout area based, at least in part, on proximity of metal segments, interconnecting segments, or a combination thereof in the layout area; performing partial re-routing in the layout area to substantially meet the criteria, wherein at least one interconnecting element is shifted or extended; and integrating the partial re-routing into the design data for use in the manufacturing processes.Type: GrantFiled: May 5, 2015Date of Patent: June 6, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Guoxiang Ning, Yuping Ren, Chin Teong Lim, Xusheng Wu, Paul Ackmann
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Patent number: 9672312Abstract: A method includes receiving a layout of an integrated circuit that includes a plurality of layers, one of the layers is selected and one or more tile number values are provided. A die area of the integrated circuit is partitioned into a plurality of tiles on the basis of the tile number values. It is determined, on the basis of the layout, if a portion of the selected one of the layers in the tile has an available space for inclusion of a test cell or a dummy cell, and a label indicative of a result is assigned to the tile. It is determined, on the basis of the labels assigned, if one or more space availability criteria are fulfilled and, if fulfilled, the labels are used for placing at least one of one or more test cells and one or more dummy cells in the layout.Type: GrantFiled: May 4, 2015Date of Patent: June 6, 2017Assignee: GLOBALFOUNDRIES Inc.Inventors: Guido Ueberreiter, Paul Ackmann, Guoxiang Ning, Jui-Hsuan Feng, Chin Teong Lim
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Patent number: 9658531Abstract: A mask is disclosed which includes a plurality of first phase shift regions disposed on a first side of the mask, and a plurality of second phase shift regions disposed on a second side of the mask. The first phase shift regions and second phase shift regions may be alternating phase shift regions in which phase shift of the first phase shift regions is out of phase, for instance by 180 degrees, from phase shift of the second phase shift regions. A method for forming the mask, and a semiconductor device fabrication method using the mask is also disclosed.Type: GrantFiled: September 3, 2014Date of Patent: May 23, 2017Assignee: GLOBALFOUNDRIES, INC.Inventors: Guoxiang Ning, Chunyu Wong, Paul Ackmann, Sarasvathi Thangaraju
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Patent number: 9645486Abstract: Methods of calibrating an OPC model using converged results of CD measurements from at least two locations along a substrate profile of a 1D, 2D, or critical area structure are provided. Embodiments include calibrating an OPC model for a structure to be formed in a substrate; simulating a CD of the structure at at least two locations along a substrate profile of the structure using the OPC model; comparing the simulated CD of the structure at each location against a corresponding measured CD; recalibrating the OPC model based on the comparing of each simulated CD against the corresponding measured CD; repeating the steps of simulating, comparing, and recalibrating until comparing at a first of the at least two locations converges to a first criteria and comparing at each other of the at least two locations converges to a corresponding criteria; and forming the structure using the recalibrated OPC model.Type: GrantFiled: December 4, 2014Date of Patent: May 9, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Chin Teong Lim, Guoxiang Ning, Paul Ackmann
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Patent number: 9535319Abstract: A method includes providing a pre-optical proximity correction (OPC) layout of at least a portion of at least one reticle. The pre-OPC layout defines a test cell including a first test cell area having a plurality of first target features having a first pitch and a second test cell area having a plurality of second target features having a second pitch. A post-OPC layout of the portion of the reticle is formed on the basis of the pre-OPC layout. The formation of the post-OPC layout includes performing a rule-based OPC process, wherein a plurality of first reticle features for the first test cell area are provided on the basis of the plurality of first target features, and performing a model-based OPC process, wherein a plurality of second reticle features for the second test cell area are provided on the basis of the plurality of second target features.Type: GrantFiled: March 31, 2015Date of Patent: January 3, 2017Assignee: GLOBALFOUNDRIES Inc.Inventors: Guido Ueberreiter, Guoxiang Ning, Jui-Hsuan Feng, Paul Ackmann, Chin Teong Lim
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Publication number: 20160363853Abstract: Pattern classification based proximity corrections for reticle fabrication are provided. A digital layout of a circuit design and proximity compensation data generated based on measurements of formed reticle elements are obtained. The proximity compensation data includes proximity correction values to correct for proximity effects of a reticle-formation process to form a reticle for use in fabricating a circuit of the circuit design. Based on a pattern classification of one or more patterns in the digital layout of the circuit design, at least one proximity correction is applied to the digital layout of the circuit design to facilitate correcting for proximity effects of the reticle-formation process, the at least one proximity correction being determined based on one or more of the proximity correction values of the obtained proximity compensation data. Additional adjustments to the digital layout are also provided according to aspects described herein.Type: ApplicationFiled: June 9, 2015Publication date: December 15, 2016Inventors: Guoxiang NING, Chin Teong LIM, Paul ACKMANN, Christian BUERGEL
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Patent number: 9500945Abstract: Pattern classification based proximity corrections for reticle fabrication are provided. A digital layout of a circuit design and proximity compensation data generated based on measurements of formed reticle elements are obtained. The proximity compensation data includes proximity correction values to correct for proximity effects of a reticle-formation process to form a reticle for use in fabricating a circuit of the circuit design. Based on a pattern classification of one or more patterns in the digital layout of the circuit design, at least one proximity correction is applied to the digital layout of the circuit design to facilitate correcting for proximity effects of the reticle-formation process, the at least one proximity correction being determined based on one or more of the proximity correction values of the obtained proximity compensation data. Additional adjustments to the digital layout are also provided according to aspects described herein.Type: GrantFiled: June 9, 2015Date of Patent: November 22, 2016Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Guoxiang Ning, Chin Teong Lim, Paul Ackmann, Christian Buergel
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Publication number: 20160328510Abstract: A method includes receiving a layout of an integrated circuit that includes a plurality of layers, one of the layers is selected and one or more tile number values are provided. A die area of the integrated circuit is partitioned into a plurality of tiles on the basis of the tile number values. It is determined, on the basis of the layout, if a portion of the selected one of the layers in the tile has an available space for inclusion of a test cell or a dummy cell, and a label indicative of a result is assigned to the tile. It is determined, on the basis of the labels assigned, if one or more space availability criteria are fulfilled and, if fulfilled, the labels are used for placing at least one of one or more test cells and one or more dummy cells in the layout.Type: ApplicationFiled: May 4, 2015Publication date: November 10, 2016Inventors: Guido Ueberreiter, Paul Ackmann, Guoxiang Ning, Jui-Hsuan Feng, Chin Teong Lim
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Publication number: 20160328511Abstract: Methods for identification and partial re-routing of selected areas (e.g., including critical areas) in a layout of an IC design and the resulting device are disclosed. Embodiments include comparing design data of an IC device against criteria of manufacturing processes to manufacture the IC device; identifying in the design data a layout area based, at least in part, on proximity of metal segments, interconnecting segments, or a combination thereof in the layout area; performing partial re-routing in the layout area to substantially meet the criteria, wherein at least one interconnecting element is shifted or extended; and integrating the partial re-routing into the design data for use in the manufacturing processes.Type: ApplicationFiled: May 5, 2015Publication date: November 10, 2016Inventors: Guoxiang NING, Yuping REN, Chin Teong LIM, Xusheng WU, Paul ACKMANN