Abstract: A structure. The structure may include a layer of cobalt disilicide that is substantially free of cobalt monosilicide and there is substantially no stringer of an oxide of titanium on the layer of cobalt disilicide. The structure may include a substrate that includes: an insulated-gate field effect transistor (FET) that includes a source, a drain, and a gate; a first layer of cobalt disilicide on the source, said first layer having substantially no cobalt monosilicide, and said first layer having substantially no stringer of an oxide of titanium thereon; a second layer of cobalt disilicide on the drain, said second layer having substantially no cobalt monosilicide having substantially no stringer of an oxide of titanium thereon; and a third layer of cobalt disilicide on the gate, said third layer having substantially no cobalt monosilicide and having substantially no stringer of an oxide of titanium thereon.

Abstract: A structure. The structure may include a layer of cobalt disilicide that is substantially free of cobalt monosilicide and there is substantially no stringer of an oxide of titanium on the layer of cobalt disilicide. The structure may include a substrate that includes: an insulated-gate field effect transistor (FET) that includes a source, a drain, and a gate; a first layer of cobalt disilicide on the source, said first layer having substantially no cobalt monosilicide, and said first layer having substantially no stringer of an oxide of titanium thereon; a second layer of cobalt disilicide on the drain, said second layer having substantially no cobalt monosilicide having substantially no stringer of an oxide of titanium thereon; and a third layer of cobalt disilicide on the gate, said third layer having substantially no cobalt monosilicide and having substantially no stringer of an oxide of titanium thereon.

Abstract: A structure relating to removal of an oxide of titanium generated as a byproduct of a process that forms cobalt disilicide within an insulated-gate field effect transistor (FET). The structure may comprise a layer of cobalt disilicide that is substantially free of cobalt monosilicide, with substantially no stringer of an oxide of titanium on the layer of cobalt disilicide. The structure may alternatively comprise a layer of cobalt disilicide, a patch of an oxide of titanium, and a reagent in contact with the patch at a temperature and for a period of time. The layer is substantially free of cobalt monosilicide. The patch is on the layer of cobalt disilicide. The reagent is adapted to remove the patch within the period of time. The reagent does not chemically react with the layer of cobalt disilicide, and the reagent comprises water, ammonium hydroxide, and hydrogen peroxide.

Abstract: A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.

Abstract: Thermal mixing methods of forming a substantially relaxed and low-defect SGOI substrate material are provided. The methods include a patterning step which is used to form a structure containing at least SiGe islands formed atop a Ge resistant diffusion barrier layer. Patterning of the SiGe layer into islands changes the local forces acting at each of the island edges in such a way so that the relaxation force is greater than the forces that oppose relaxation. The absence of restoring forces at the edges of the patterned layers allows the final SiGe film to relax further than it would if the film was continuous.

Abstract: Methods for preventing cavitation in high aspect ratio dielectric regions in a semiconductor device, and the device so formed, are disclosed. The invention includes depositing a first dielectric in the high aspect ratio dielectric region between a pair of structures, and then removing the first dielectric to form a bearing surface adjacent each structure. The bearing surface prevents cavitation of the interlayer dielectric that subsequently fills the high aspect ratio region.

Abstract: Disclosed is a method and system of forming an integrated circuit transistor having a reduced gate height that forms a laminated structure having a substrate, a gate conductor above the substrate, and at least one sacrificial layer above the gate conductor. The process patterns the laminated structure into at least one gate stack extending from the substrate, forms spacers adjacent to the gate stack, dopes regions of the substrate not protected by the spacers to form source and drain regions adjacent the gate stack, and removes the spacers and the sacrificial layer.

Abstract: A method and structure for a CMOS device comprises depositing a silicon over insulator (SOI) wafer over a buried oxide (BOX) substrate, wherein the SOI wafer has a predetermined thickness; forming a gate dielectric over the SOI wafer; forming a shallow trench isolation (STI) region over the BOX substrate, wherein the STI region is configured to have a generally rounded corner; forming a gate structure over the gate dielectric; depositing an implant layer over the SOI wafer; performing one of N-type and P-type dopant implantations in the SOI wafer and the implant layer; and heating the device to form source and drain regions from the implant layer and the SOI wafer, wherein the source and drain regions have a thickness greater than the predetermined thickness of the SOI wafer, wherein the gate dielectric is positioned lower than the STI region.

Abstract: A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.

Abstract: A method for removing a formation of oxide of titanium that is generated as a by product of a process that forms cobalt disilicide within an insulated-gate field effect transistor (FET). The method applies a chemical reagent to the FET at a predetermined temperature, and for a predetermined period of time, necessary for removing the formation, wherein the reagent does not chemically react with the cobalt disilicide. A reagent that accomplishes this task comprises water (H2O), ammonium hydroxide (NH4OH), and hydrogen peroxide (H2O2), wherein the NH4OH and the H2O2 each comprise approximately 4% of the total reagent volume. An effective temperature is 65 ° C. combined with a 3 minute period of application.

Abstract: A method for removing a formation of oxide of titanium that is generated as a byproduct of a process that forms cobalt disilicide within an insulated-gate field effect transistor (FET). The method applies a chemical reagent to the FET at a predetermined temperature, and for a predetermined period of time, necessary for removing the formation, wherein the reagent does not chemically react with the cobalt disilicide. A reagent that accomplishes this task comprises water (H2O), ammonium hydroxide (NH4OH), and hydrogen peroxide (H2O2), wherein the NH4OH and the H2O2 each comprise approximately 4% of the total reagent volume. An effective temperature is 65° C. combined with a 3 minute period of application.