Abstract: Embodiments of the present invention are directed to methods, systems, and circuitry for reduced error in power consumption estimation for distinct circuitries. A non-limiting example includes distinct circuitry having an optimized power consumption definition. The distinct circuitry includes a substrate. The distinct circuitry includes an arrangement of interoperable hardware components disposed on the substrate having input pins defined according to a model described by a hardware description language operable to emulate toggle events of the interoperable hardware components defined by the model having a toggle event count based on combinations of the toggle events that correspond to predetermined power quantities. The toggle events define an aggregate toggle power consumption closer to an actual power consumption than an aggregate pin power consumption based on the input pins.

Abstract: A method for testing a circuit includes receiving, by a noise injection circuit, an input signal and generating a noise pulse. Generating the noise pulse includes computing an input resistor pulse, and computing an output resistor pulse. Generating the noise pulse further includes short-circuiting an output resistor substantially simultaneously with opening an input resistor. The method for testing the circuit includes modifying, by the noise injection circuit, the input signal using the noise pulse.

Abstract: An aspect a bit selection path configured to propagate a bit selection signal. The bit selection path includes bit selection delay circuitry defining a bit selection delay. The memory array includes a row selection path configured to propagate a row selection signal. The row selection path includes row selection delay circuitry defining a row selection delay. The memory array includes local selection circuitry. The local selection circuitry is configured to receive the bit selection signal from the bit selection path before the row selection signal from the row selection path according to the bit selection delay and the row selection delay.

Abstract: An aspect a bit selection path configured to propagate a bit selection signal. The bit selection path includes bit selection delay circuitry defining a bit selection delay. The memory array includes a row selection path configured to propagate a row selection signal. The row selection path includes row selection delay circuitry defining a row selection delay. The memory array includes local selection circuitry. The local selection circuitry is configured to receive the bit selection signal from the bit selection path before the row selection signal from the row selection path according the bit selection delay and the row selection delay.

Abstract: A method for testing a circuit includes receiving, by a noise injection circuit, an input signal and generating a noise pulse. Generating the noise pulse includes computing an input resistor pulse, and computing an output resistor pulse. Generating the noise pulse further includes short-circuiting an output resistor substantially simultaneously with opening an input resistor. The method for testing the circuit includes modifying, by the noise injection circuit, the input signal using the noise pulse.

Abstract: Embodiments of the present invention are directed to methods, systems, and circuitry for reduced error in power consumption estimation for distinct circuitries. A non-limiting example includes distinct circuitry having an optimized power consumption definition. The distinct circuitry includes a substrate. The distinct circuitry includes an arrangement of interoperable hardware components disposed on the substrate having input pins defined according to a model described by a hardware description language operable to emulate toggle events of the interoperable hardware components defined by the model having a toggle event count based on combinations of the toggle events that correspond to predetermined power quantities. The toggle events define an aggregate toggle power consumption closer to an actual power consumption than an aggregate pin power consumption based on the input pins.

Abstract: According to one or more embodiments of the present invention, a delay circuit includes a first sub-circuit that delays a leading edge of an input signal according to first control settings, the input signal being for an electric device. The delay circuit further includes a second sub-circuit that delays a trailing edge of the input signal according to second control settings. An output signal from the delay circuit is received by the electric device.

Abstract: A plurality of dynamic decode circuits for decoding a plurality of input signals comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the plurality of dynamic decode circuits sharing a conditioned node.

Abstract: A method for decoding a plurality of input signals in a plurality of dynamic decode circuits, each dynamic decode circuit sharing a conditioned node and comprising a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate.

Abstract: A method for a dynamic decode circuit to decode a plurality of input signals, the dynamic decode circuit comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the interconnection of the pair of serially connected transistors is precharged when the evaluation clock is inactive.

Abstract: A dynamic decode circuit for decoding a plurality of input signals comprises precharge circuits that consist of two serially connected transistors, that utilize an evaluate clock and a delayed evaluate clock, that delay the start of a precharge phase for a predetermined period after the end of an evaluation phase.

Abstract: A dynamic decode circuit for decoding a plurality of input signals comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the interconnection of the pair of serially connected transistors is precharged when the evaluation clock is inactive to provide a delay between the end of the active evaluation clock and the beginning of the precharge.

Abstract: A plurality of dynamic decode circuits for decoding a plurality of input signals comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the plurality of dynamic decode circuits sharing a conditioned node.

Abstract: A dynamic decode circuit for decoding a plurality of input signals comprises precharge circuits that consist of two serially connected transistors, that utilize an evaluate clock and a delayed evaluate clock, that delay the start of a precharge phase for a predetermined period after the end of an evaluation phase.

Abstract: A method for a dynamic decode circuit to decode a plurality of input signals, the dynamic decode circuit comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the interconnection of the pair of serially connected transistors is precharged when the evaluation clock is inactive.

Abstract: A method for decoding a plurality of input signals in a plurality of dynamic decode circuits, each dynamic decode circuit sharing a conditioned node and comprising a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate.

Abstract: A dynamic decode circuit for decoding a plurality of input signals comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the interconnection of the pair of serially connected transistors is precharged when the evaluation clock is inactive to provide a delay between the end of the active evaluation clock and the beginning of the precharge.

Abstract: A dynamic decode circuit for decoding a plurality of input signals comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the interconnection of the pair of serially connected transistors is precharged when the evaluation clock is inactive to provide a delay between the end of the active evaluation clock and the beginning of the precharge.

Abstract: A dynamic decode circuit for decoding a plurality of input signals comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the interconnection of the pair of serially connected transistors is precharged when the evaluation clock is inactive to provide a delay between the end of the active evaluation clock and the beginning of the precharge.

Abstract: A dynamic decode circuit for decoding a plurality of input signals comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the interconnection of the pair of serially connected transistors is precharged when the evaluation clock is inactive to provide a delay between the end of the active evaluation clock and the beginning of the precharge.