Patents by Inventor Paul Alan McConnelee
Paul Alan McConnelee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11605609Abstract: A package structure includes a first dielectric layer, semiconductor device(s) attached to the first dielectric layer, and an embedding material applied to the first dielectric layer so as to embed the semiconductor device therein, the embedding material comprising one or more additional dielectric layers. Vias are formed through the first dielectric layer to the at least one semiconductor device, with metal interconnects formed in the vias to form electrical interconnections to the semiconductor device. Input/output (I/O) connections are located on one end of the package structure on one or more outward facing surfaces thereof to provide a second level connection to an external circuit. The package structure interfits with a connector on the external circuit to mount the package perpendicular to the external circuit, with the I/O connections being electrically connected to the connector to form the second level connection to the external circuit.Type: GrantFiled: February 12, 2020Date of Patent: March 14, 2023Assignee: General Electric CompanyInventors: Arun Virupaksha Gowda, Paul Alan McConnelee, Shakti Singh Chauhan
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Patent number: 11177204Abstract: An electronics package is disclosed herein that includes a glass substrate having an exterior portion surrounding an interior portion thereof, wherein the interior portion has a first thickness and the exterior portion has a second thickness larger than the first thickness. An adhesive layer is formed on a lower surface of the interior portion of the glass substrate. A semiconductor device having an upper surface is coupled to the adhesive layer, the semiconductor device having at least one contact pad disposed on the upper surface thereof. A first metallization layer is coupled to an upper surface of the glass substrate and extends through a first via formed through the first thickness of the glass substrate to couple with the at least one contact pad of the semiconductor device.Type: GrantFiled: June 21, 2019Date of Patent: November 16, 2021Assignee: General Electric CompanyInventors: Arun Virupaksha Gowda, Paul Alan McConnelee, Nancy Cecelia Stoffel, Risto Ilkka Tuominen
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Publication number: 20200185349Abstract: A package structure includes a first dielectric layer, semiconductor device(s) attached to the first dielectric layer, and an embedding material applied to the first dielectric layer so as to embed the semiconductor device therein, the embedding material comprising one or more additional dielectric layers. Vias are formed through the first dielectric layer to the at least one semiconductor device, with metal interconnects formed in the vias to form electrical interconnections to the semiconductor device. Input/output (I/O) connections are located on one end of the package structure on one or more outward facing surfaces thereof to provide a second level connection to an external circuit. The package structure interfits with a connector on the external circuit to mount the package perpendicular to the external circuit, with the I/O connections being electrically connected to the connector to form the second level connection to the external circuit.Type: ApplicationFiled: February 12, 2020Publication date: June 11, 2020Inventors: Arun Virupaksha Gowda, Paul Alan McConnelee, Shakti Singh Chauhan
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Patent number: 10607957Abstract: A package structure includes a first dielectric layer, semiconductor device(s) attached to the first dielectric layer, and an embedding material applied to the first dielectric layer so as to embed the semiconductor device therein, the embedding material comprising one or more additional dielectric layers. Vias are formed through the first dielectric layer to the at least one semiconductor device, with metal interconnects formed in the vias to form electrical interconnections to the semiconductor device. Input/output (I/O) connections are located on one end of the package structure on one or more outward facing surfaces thereof to provide a second level connection to an external circuit. The package structure interfits with a connector on the external circuit to mount the package perpendicular to the external circuit, with the I/O connections being electrically connected to the connector to form the second level connection to the external circuit.Type: GrantFiled: October 11, 2017Date of Patent: March 31, 2020Assignee: General Electric CompanyInventors: Arun Virupaksha Gowda, Paul Alan McConnelee, Shakti Singh Chauhan
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Patent number: 10453786Abstract: An electronics package is disclosed herein that includes a glass substrate having an exterior portion surrounding an interior portion thereof, wherein the interior portion has a first thickness and the exterior portion has a second thickness larger than the first thickness. An adhesive layer is formed on a lower surface of the interior portion of the glass substrate. A semiconductor device having an upper surface is coupled to the adhesive layer, the semiconductor device having at least one contact pad disposed on the upper surface thereof. A first metallization layer is coupled to an upper surface of the glass substrate and extends through a first via formed through the first thickness of the glass substrate to couple with the at least one contact pad of the semiconductor device.Type: GrantFiled: January 19, 2016Date of Patent: October 22, 2019Assignee: General Electric CompanyInventors: Arun Virupaksha Gowda, Paul Alan McConnelee, Nancy Cecelia Stoffel, Risto Ilkka Tuominen
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Publication number: 20190311981Abstract: An electronics package is disclosed herein that includes a glass substrate having an exterior portion surrounding an interior portion thereof, wherein the interior portion has a first thickness and the exterior portion has a second thickness larger than the first thickness. An adhesive layer is formed on a lower surface of the interior portion of the glass substrate. A semiconductor device having an upper surface is coupled to the adhesive layer, the semiconductor device having at least one contact pad disposed on the upper surface thereof. A first metallization layer is coupled to an upper surface of the glass substrate and extends through a first via formed through the first thickness of the glass substrate to couple with the at least one contact pad of the semiconductor device.Type: ApplicationFiled: June 21, 2019Publication date: October 10, 2019Inventors: Arun Virupaksha Gowda, Paul Alan McConnelee, Nancy Cecelia Stoffel, Risto Ilkka Tuominen
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Patent number: 10276486Abstract: A chip package is disclosed that includes an electronic chip having a plurality of die pads formed on a top surface thereof, with a polyimide flex layer positioned thereon by way of an adhesive layer. A plurality of vias is formed through the polyimide flex layer and the adhesive layer corresponding to the die pads. A plurality of metal interconnects are formed on the polyimide flex layer each having a cover pad covering a portion of a top surface of the polyimide flex layer, a sidewall extending down from the cover pad and through the via along a perimeter thereof, and a base connected to the sidewall and forming an electrical connection with a respective die pad. Each of the base and the sidewall is formed to have a thickness that is equal to or greater than a thickness of the adhesive layer.Type: GrantFiled: March 2, 2010Date of Patent: April 30, 2019Assignee: General Electric CompanyInventors: Thomas Bert Gorczyca, Richard Joseph Saia, Paul Alan McConnelee
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Patent number: 10269688Abstract: A semiconductor device module includes a dielectric layer, a semiconductor device having a first surface coupled to the dielectric layer, and a conducting shim having a first surface coupled to the dielectric layer. The semiconductor device also includes an electrically conductive heatspreader having a first surface coupled to a second surface of the semiconductor device and a second surface of the conducting shim. A metallization layer is coupled to the first surface of the semiconductor device and the first surface of the conducting shim. The metallization layer extends through the dielectric layer and is electrically connected to the second surface of the semiconductor device by way of the conducting shim and the heatspreader.Type: GrantFiled: May 20, 2013Date of Patent: April 23, 2019Assignee: General Electric CompanyInventors: Arun Virupaksha Gowda, Paul Alan McConnelee, Shakti Singh Chauhan
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Patent number: 10204881Abstract: A power overlay (POL) structure includes a power device having at least one upper contact pad disposed on an upper surface of the power device, and a POL interconnect layer having a dielectric layer coupled to the upper surface of the power device and a metallization layer having metal interconnects extending through vias formed through the dielectric layer and electrically coupled to the at least one upper contact pad of the power device. The POL structure also includes at least one copper wirebond directly coupled to the metallization layer.Type: GrantFiled: March 29, 2017Date of Patent: February 12, 2019Assignee: General Electric CompanyInventors: Arun Virupaksha Gowda, Paul Alan McConnelee
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Patent number: 10186477Abstract: A semiconductor device module includes a dielectric layer, a semiconductor device having a first surface coupled to the dielectric layer, and a conducting shim having a first surface coupled to the dielectric layer. The semiconductor device also includes an electrically conductive heatspreader having a first surface coupled to a second surface of the semiconductor device and a second surface of the conducting shim. A metallization layer is coupled to the first surface of the semiconductor device and the first surface of the conducting shim. The metallization layer extends through the dielectric layer and is electrically connected to the second surface of the semiconductor device by way of the conducting shim and the heatspreader.Type: GrantFiled: November 29, 2016Date of Patent: January 22, 2019Assignee: General Electric CompanyInventors: Arun Virupaksha Gowda, Paul Alan McConnelee, Shakti Singh Chauhan
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Patent number: 10141203Abstract: An electronics package includes a lower insulating layer, an upper insulating layer coupled to the lower insulating layer, and a conductive contact pad coupled to a second surface of the upper insulating layer. An electrical component is positioned within an opening formed through the upper insulating layer. A first interconnect layer extends through at least one via in the lower insulating layer to electrically couple with at least one contact pad on the electrical component and a second interconnect layer extends through at least one via in the upper insulating layer and electrically couples the first interconnect layer to the conductive contact pad.Type: GrantFiled: November 30, 2017Date of Patent: November 27, 2018Assignee: General Electric CompanyInventors: Paul Alan McConnelee, Arun Virupaksha Gowda
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Patent number: 10141251Abstract: An electronic package is provided. The electronic package includes a substrate and a plurality of vias defined by a corresponding plurality of pre-defined via patterns. The electronic package further a metal built-up layer disposed on portions of the substrate to provide a plurality of pre-defined via locations and the plurality of pre-defined via patterns of the plurality of vias. Also, the electronic package includes a first conductive layer disposed on at least a portion of the metal built-up layer. Moreover, the electronic package includes a second conductive layer disposed on the first conductive layer, where the plurality of vias is disposed at least in part in the metal built-up layer, the first conductive layer, and the second conductive layer.Type: GrantFiled: December 23, 2014Date of Patent: November 27, 2018Assignee: GENERAL ELECTRIC COMPANYInventors: Arun Virupaksha Gowda, Paul Alan McConnelee, Risto Ilkka Tuominen
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Patent number: 10068840Abstract: An electrical interconnect assembly for use in an integrated circuit package includes a mounting substrate having a thickness defined between a first surface and a second surface thereof and at least one electrically conductive pad formed on the first surface of the mounting substrate. A metallization layer coats a surface of the at least one electrically conductive pad and is electrically coupled thereto. The metallization layer also coats portion of the first surface of the mounting substrate and extends through at least one via formed through the thickness of the mounting substrate. A method of manufacturing an electrical interconnect assembly includes forming at least one top side contact pad on a top surface of a mounting substrate and depositing a metallization layer on the top side contact pad(s), on an exposed portion of the top surface, and into via(s) formed through a thickness of the mounting substrate.Type: GrantFiled: June 9, 2017Date of Patent: September 4, 2018Assignee: General Electric CompanyInventors: Paul Alan McConnelee, Kevin Matthew Durocher, Scott Smith, Donald Paul Cunningham
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Patent number: 9953917Abstract: An electronics package includes an insulating substrate, a semiconductor device having a top surface coupled to a first side of the insulating substrate, and a pass-through structure coupled to the first side of the insulating substrate. The pass-through structure includes an insulating core, a resistor disposed proximate a top surface of the insulating core, and at least one through-hole structure forming at least one conductive pathway through a thickness of the insulating core. A patterned metallization layer is formed on a second side of the insulating substrate. The patterned metallization layer is electrically coupled to at least one first conductive pad of the semiconductor device and electrically couples at least one second conductive pad of the semiconductor device to a through-hole structure of the at least one through-hole structure through the resistor.Type: GrantFiled: December 12, 2016Date of Patent: April 24, 2018Assignee: General Electric CompanyInventors: Arun Virupaksha Gowda, Raymond Albert Fillion, Paul Alan McConnelee
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Patent number: 9953913Abstract: An electronics package includes an insulating substrate, a semiconductor device having a top surface coupled to a first side of the insulating substrate, and a pass-through component coupled to the first side of the insulating substrate. The pass-through component includes an insulating core and at least one through-hole structure comprising a conductive body extending through the thickness of the insulating core. A metallization layer is formed on a second side of the insulating substrate and extends through at least one via in the insulating substrate to electrically couple at least one conductive pad on the top surface of the semiconductor device to the at least one through-hole structure. An insulating material surrounds the semiconductor device and the insulating core of the pass-through component.Type: GrantFiled: December 12, 2016Date of Patent: April 24, 2018Assignee: General Electric CompanyInventors: Arun Virupaksha Gowda, Raymond Albert Fillion, Paul Alan McConnelee
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Publication number: 20180082857Abstract: An electronics package includes a lower insulating layer, an upper insulating layer coupled to the lower insulating layer, and a conductive contact pad coupled to a second surface of the upper insulating layer. An electrical component is positioned within an opening formed through the upper insulating layer. A first interconnect layer extends through at least one via in the lower insulating layer to electrically couple with at least one contact pad on the electrical component and a second interconnect layer extends through at least one via in the upper insulating layer and electrically couples the first interconnect layer to the conductive contact pad.Type: ApplicationFiled: November 30, 2017Publication date: March 22, 2018Inventors: Paul Alan McConnelee, Arun Virupaksha Gowda
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Publication number: 20180033762Abstract: A package structure includes a first dielectric layer, semiconductor device(s) attached to the first dielectric layer, and an embedding material applied to the first dielectric layer so as to embed the semiconductor device therein, the embedding material comprising one or more additional dielectric layers. Vias are formed through the first dielectric layer to the at least one semiconductor device, with metal interconnects formed in the vias to form electrical interconnections to the semiconductor device. Input/output (I/O) connections are located on one end of the package structure on one or more outward facing surfaces thereof to provide a second level connection to an external circuit. The package structure interfits with a connector on the external circuit to mount the package perpendicular to the external circuit, with the I/O connections being electrically connected to the connector to form the second level connection to the external circuit.Type: ApplicationFiled: October 11, 2017Publication date: February 1, 2018Inventors: Arun Virupaksha Gowda, Paul Alan McConnelee, Shakti Singh Chauhan
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Patent number: 9847236Abstract: An electronics package includes a lower insulating layer, an upper insulating layer coupled to the lower insulating layer, and a conductive contact pad coupled to a second surface of the upper insulating layer. An electrical component is positioned within an opening formed through the upper insulating layer. A first interconnect layer extends through at least one via in the lower insulating layer to electrically couple with at least one contact pad on the electrical component and a second interconnect layer extends through at least one via in the upper insulating layer and electrically couples the first interconnect layer to the conductive contact pad.Type: GrantFiled: May 15, 2017Date of Patent: December 19, 2017Assignee: General Electric CompanyInventors: Paul Alan McConnelee, Arun Virupaksha Gowda
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Patent number: 9806051Abstract: A package structure includes a first dielectric layer, semiconductor device(s) attached to the first dielectric layer, and an embedding material applied to the first dielectric layer so as to embed the semiconductor device therein, the embedding material comprising one or more additional dielectric layers. Vias are formed through the first dielectric layer to the at least one semiconductor device, with metal interconnects formed in the vias to form electrical interconnections to the semiconductor device. Input/output (I/O) connections are located on one end of the package structure on one or more outward facing surfaces thereof to provide a second level connection to an external circuit. The package structure interfits with a connector on the external circuit to mount the package perpendicular to the external circuit, with the I/O connections being electrically connected to the connector to form the second level connection to the external circuit.Type: GrantFiled: March 4, 2014Date of Patent: October 31, 2017Assignee: General Electric CompanyInventors: Arun Virupaksha Gowda, Paul Alan McConnelee, Shakti Singh Chauhan
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Publication number: 20170278782Abstract: An electrical interconnect assembly for use in an integrated circuit package includes a mounting substrate having a thickness defined between a first surface and a second surface thereof and at least one electrically conductive pad formed on the first surface of the mounting substrate. A metallization layer coats a surface of the at least one electrically conductive pad and is electrically coupled thereto. The metallization layer also coats portion of the first surface of the mounting substrate and extends through at least one via formed through the thickness of the mounting substrate.Type: ApplicationFiled: June 9, 2017Publication date: September 28, 2017Inventors: Paul Alan McConnelee, Kevin Matthew Durocher, Scott Smith, Donald Paul Cunningham