Abstract: Embodiments of the invention are directed to a computer-implemented method of operating a data transmission system. The data transmission system includes a transmitter and a receiver. The computer-implemented method includes using the transmitter to send serialized data from the transmitter through a plurality of lanes to the receiver. The transmitter sends the serialized data at a first serialization ratio. The receiver is configured to receive and load the serialized data at a second deserialization ratio, wherein the first serialization ration is greater than the second deserialization ratio.

Abstract: A computer-implemented method includes using a transmitter to send data from the transmitter through a plurality of lanes to a receiver using a synchronous operation mode that includes sending the data from the transmitter through the plurality of lanes to the receiver in a synchronous transmission manner that relies on an alignment between a transmitter clock frequency and a receiver clock frequency. A synchronous operation performance analysis (SOPA) is performed during the synchronous operation mode. A switch from the synchronous operation mode to an asynchronous operation mode is made based on a result of performing the SOPA. The asynchronous operation mode includes sending the data from the transmitter through the plurality of lanes to the receiver without requiring alignment between the transmitter clock frequency and the receiver clock frequency.

Abstract: Embodiments of the invention are directed to a computer-implemented method of operating a data transmission system. The data transmission system includes a transmitter and a receiver. The computer-implemented method includes using the transmitter to send serialized data from the transmitter through a plurality of lanes to the receiver. The transmitter sends the serialized data at a first serialization ratio. The receiver is configured to receive and load the serialized data at a second deserialization ratio, wherein the first serialization ration is greater than the second deserialization ratio.

Abstract: A computer-implemented method includes using a transmitter to send data from the transmitter through a plurality of lanes to a receiver using a synchronous operation mode that includes sending the data from the transmitter through the plurality of lanes to the receiver in a synchronous transmission manner that relies on an alignment between a transmitter clock frequency and a receiver clock frequency. A synchronous operation performance analysis (SOPA) is performed during the synchronous operation mode. A switch from the synchronous operation mode to an asynchronous operation mode is made based on a result of performing the SOPA. The asynchronous operation mode includes sending the data from the transmitter through the plurality of lanes to the receiver without requiring alignment between the transmitter clock frequency and the receiver clock frequency.

Abstract: A method, an apparatus, and a computer program are provided to account for data stored in Dynamic Random Access Memory (DRAM) write buffers. There is difficulty in tracking the data stored in DRAM write buffers. To alleviate the difficulty, a cache line list is employed. The cache line list is maintained in a memory controller, which is updated with data movement. This list allows for ease of maintenance of data without loss of consistency.

Abstract: A mechanism is provided to reuse functional data buffers. With Extreme Data Rate (XDR™) Dynamic Random Access Memory (DRAM), test patterns are employed to dynamically calibrate data with the clock. To perform this task, data buffers are employed to store data and commands for the calibration patterns. However, there are different procedures and requirements for transmission and reception calibrations. Hence, to reduce the amount of hardware needed to perform transmission and reception calibrations, the data buffers employ additional front end circuitry to reuse the buffers for both tasks.

Abstract: The present invention generally relates to memory controllers operating in a system containing a variable system clock. The memory controller may exchange data with a processor operating at a variable processor clock frequency. However the memory controller may perform memory accesses at a constant memory clock frequency. Asynchronous buffers may be provided to transfer data across the variable and constant clock domains. To prevent read buffer overflow while switching to a lower processor clock frequency, the memory controller may quiesce the memory sequencers and pace read data from the sequencers at a slower rate. To prevent write data under runs, the memory controller's data flow logic may perform handshaking to ensure that write data is completely received in the buffer before performing a write access.

Abstract: Managing write-to-read turnarounds in an early read after write memory system is presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank.

Abstract: Separate handling of read and write operations of Read-Modify-Write Commands in an XDR™ memory system is provided. This invention allows the system to issue other commands between the reads and writes of a RMW. This insures that the dataflow time from read to write is not a penalty. A RMW buffer is used to store the read data and a write buffer is used to store the write data. A MUX is used to merge the read data and the write data, and transmit the merged data to the target DRAM via the XIO. The RMW buffer can also be used for scrubbing commands.

Abstract: Separate handling of read and write operations of Read-Modify-Write Commands in an XDR™ memory system is provided. This invention allows the system to issue other commands between the reads and writes of a RMW. This insures that the dataflow time from read to write is not a penalty. A RMW buffer is used to store the read data and a write buffer is used to store the write data. A MUX is used to merge the read data and the write data, and transmit the merged data to the target DRAM via the XIO. The RMW buffer can also be used for scrubbing commands.

Abstract: A method, apparatus and computer program product are provided for implementing packet command instructions for network processing. A set of packet commands is provided. Each packet command defines a corresponding packet operation. A command from the set of packet commands is issued to perform the defined corresponding packet operation. A packet buffer structure hardware is provided for performing one or more predefined packet manipulation functions responsive to the issued command.

Abstract: Managing write-to-read turnarounds in an early read after write memory system is presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank.

Abstract: Managing write-to-read turnarounds in an early read after write memory system is presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank.

Abstract: The present invention generally relates to memory controllers operating in a system containing a variable system clock. The memory controller may exchange data with a processor operating at a variable processor clock frequency. However the memory controller may perform memory accesses at a constant memory clock frequency. Asynchronous buffers may be provided to transfer data across the variable and constant clock domains. To prevent read buffer overflow while switching to a lower processor clock frequency, the memory controller may quiesce the memory sequencers and pace read data from the sequencers at a slower rate. To prevent write data under runs, the memory controller's data flow logic may perform handshaking to ensure that write data is completely received in the buffer before performing a write access.

Abstract: The present invention generally relates to memory controllers operating in a system containing a variable system clock. The memory controller may exchange data with a processor operating at a variable processor clock frequency. However the memory controller may perform memory accesses at a constant memory clock frequency. Asynchronous buffers may be provided to transfer data across the variable and constant clock domains. To prevent read buffer overflow while switching to a lower processor clock frequency, the memory controller may quiesce the memory sequencers and pace read data from the sequencers at a slower rate. To prevent write data under runs, the memory controller's data flow logic may perform handshaking to ensure that write data is completely received in the buffer before performing a write access.

Abstract: In a first aspect, a first method of interfacing a processor and memory is provided. The first method includes the steps of (1) providing a processor adapted to issue a command complying with a first protocol; (2) providing a memory coupled to the processor and accessible by a command complying with a second protocol; (3) employing a plurality of scrub commands complying with the second protocol to check respective portions of the memory for errors, wherein each scrub command complying with the second protocol is a converted version of a scrub command complying with the first protocol issued by the processor and the respective portions are non-sequential; and (4) refreshing bits stored in the entire memory within a predetermined time period. Numerous other aspects are provided.

Abstract: In a first aspect, a first method of interfacing a processor and memory is provided. The first method includes the steps of (1) providing a computer system including (a) a memory; (b) a processor adapted to issue a functional command to the memory; (c) a translation chip; (d) a first link adapted to couple the processor to the translation chip; and (e) a second link adapted to couple the translation chip to the memory; (2) calibrating the first link using the translation chip; and (3) while calibrating the first link, calibrating the second link using the translation chip. Numerous other aspects are provided.

Abstract: In a first aspect, a first method of interfacing a processor and memory is provided. The first method includes the steps of (1) providing a computer system including (a) a first memory; (b) a processor adapted to issue a functional command to the first memory; (c) a translation chip; (d) a cache memory coupled to the translation chip; (e) a first link adapted to couple the processor to the translation chip; and (f) a second link adapted to couple the translation chip to the first memory; and (2) calibrating the first link to transmit data between the processor and cache memory. Numerous other aspects are provided.

Abstract: Separate handling of read and write operations of Read-Modify-Write Commands in an XDR™ memory system is provided. This invention allows the system to issue other commands between the reads and writes of a RMW. This insures that the dataflow time from read to write is not a penalty. A RMW buffer is used to store the read data and a write buffer is used to store the write data. A MUX is used to merge the read data and the write data, and transmit the merged data to the target DRAM via the XIO. The RMW buffer can also be used for scrubbing commands.

Abstract: A method, an apparatus, and a computer program are provided to reuse functional data buffers. With Extreme Data Rate (XDR™) Dynamic Random Access Memory (DRAM), test patterns are employed to dynamically calibrate data with the clock. To perform this task, data buffers are employed to store data and commands for the calibration patterns. However, there are different procedures and requirements for transmission and reception calibrations. Hence, to reduce the amount of hardware needed to perform transmission and reception calibrations, the data buffers employ additional front end circuitry to reuse the buffers for both tasks.