Abstract: An on-chip watchdog circuit (100) is provided that generates an output signal (175) when an error signal (112) generated by a circuit under test (110) is detected. The on-chip watchdog circuit (100) comprises a logic gate (125) that is connected to a clock signal and receives a signal in response to the error signal 112 generated by the circuit under test (110). A gate output circuit (140) is connected to an output of the logic gate (125). An RC circuit (150) is connected to the gate output circuit (140). A comparator (170) is connected to the RC circuit (150). The comparator (170) is also connected to a voltage divider (160) and provides the output signal (175) in response to the error signal (112) generated by the circuit under test (110), and the on-chip watchdog circuit (100) and the circuit under test (110) are integrated on a same semiconductor microchip.

Abstract: A circuit and method for achieving hold time compatibility between data-source devices coupled to a data-requesting device through a data bus is provided. The circuit is made up of an impedance coupled to the data bus, and the value of that impedance is selected, based on a respective capacitance in the data bus, to introduce a predetermined delay to data passing therethrough.

Abstract: An apparatus and method used to calibrate a gamma camera include an energy source and intensity selector and an energy weighting device. The energy source provides an energy output, such as an electrical current. The intensity selector is connected to the energy source and adjusts the energy output to a predetermined energy level that corresponds to an intensity of a predetermined radioactive source. The energy weighting device is also connected to the energy source and gamma camera, and the spatial compensator creates calibration signals from the energy output of the energy source. The calibration signals are supplied to the gamma camera and used during calibration of the gamma camera in lieu of energy signals produced by the gamma camera in response to a radioactive source.

Abstract: An on-chip watchdog circuit is provided that generates an output signal when an error signal generated by a circuit under test is detected. The on-chip watchdog circuit comprises a logic gate that is connected to a clock signal and receives a signal in response to the error signal generated by the circuit under test. A gate output circuit is connected to an output of the logic gate. An RC circuit is connected to the gate output circuit. A voltage divider is connected to the RC circuit. A comparator is connected to the voltage divider and provides the output signal in response to the error signal generated by the circuit under test, and the on-chip watchdog circuit and the circuit under test are integrated on a same semiconductor microchip.

Abstract: The present invention provides a clocked comparator which extends the time period before an input signal is measured to include most of the clock cycle, thereby increasing the amount of time available for the input signal to achieve a “steady-state” condition. After the input signal achieves a “steady-state” condition the comparator compares the input signal against a reference voltage and a decision register latches the comparator output. The decision signal may then be further latched to be made available for external circuitry in the subsequent clock cycle. A multi-phase programmable signal generator is connected to the clocked generator for generating a plurality of timing signals. The multi-phase programmable signal generator employs a plurality of single bit registers interconnected in series to form a shift register. Output signals generated by the programmable signal generator are used to drive the switches and register clocks of the clocked comparator.

Abstract: In embodiments of the present invention, an energy extractor includes a capacitor which experiences capacitance and voltage changes in response to movement of a capacitor plate or of a dielectric material. In one embodiment, a third plate is positioned between first and second plates to create two capacitors of varying capacitances. In another embodiment, one capacitor plate is attached by flexible arms which permit movement across another capacitor plate. The above capacitors can be used singularly or with one or more other capacitors and are rectified either individually or in a cascaded arrangement for supplying power to a rechargeable energy source. The above capacitors can be fabricated on a substrate along with supporting electronics such as diodes.

Abstract: A programmable clock circuit generates a plurality of phase clock signals in correspondence with an associated control word programmed into a memory. Programmable clock circuit is implemented digitally in an application specific integrated circuit. Each phase clock signal is synchronized by a master clock signal which reduces signal jitter and improves phase signal accuracy.

Abstract: The present invention provides a clocked comparator which extends the time period before an input signal is measured to include most of the clock cycle, thereby increasing the amount of time available for the input signal to achieve a "steady-state" condition. After the input signal achieves a "steady-state" condition the comparator compares the input signal against a reference voltage and a decision register latches the comparator output. The decision signal may then be further latched to be made available for external circuitry in the subsequent clock cycle. A multi-phase programmable signal generator is connected to the clocked generator for generating a plurality of timing signals. The multi-phase programmable signal generator employs a plurality of single bit registers interconnected in series to form a shift register. Output signals generated by the programmable signal generator are used to drive the switches and register clocks of the clocked comparator.

Abstract: A delta sigma modulator having reduced quiescent power consumption as compared to known delta sigma modulators utilizes no operational amplifiers and includes, in one embodiment, an input CCD and a summing CCD coupled to the output of the input CCD. A readout is connected to receive output signals from the summing CCD. Both an integration/recirculation input CCD and a comparator are provided to receive output signals from the readout. The integration/recirculation input CCD feeds back a charge to the summing CCD, and the output of the comparator is connected to a fill and spill reference CCD, which also feeds back a charge to the summing CCD. The comparator output signal is an oversampled digitized version of the analog signal sampled by the input CCD. The comparator output signal is supplied to a low pass digital filter, and a decimator is connected to the output of the digital filter.