Patents by Inventor Paul Andry

Paul Andry has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10166632
    Abstract: A method for aligning a scan laser beam on a wafer include scanning a scan laser beam across a laser beam sensor along a scan line, picking up a scan laser beam, at a first position, using a first optical slit of the laser beam sensor to generate a first electrical pulse, picking up the scan laser beam, at a second position, using a second optical slit of the laser beam sensor to generate a second electrical pulse, picking up the scan laser beam, at a third position, using a third optical slit of the laser beam sensor to generate a third electrical pulse, and determining a spot size and a position of the laser beam based on the first to third electrical pulses.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Russell Budd, Robert Polastre, Paul Andry
  • Patent number: 10118250
    Abstract: A method and system for aligning a scan laser beam on a wafer include scanning a scan laser beam across a laser beam sensor along a scan line, picking up a scan laser beam, at a first position, using a first optical slit of the laser beam sensor to generate a first electrical pulse, picking up the scan laser beam, at a second position, using a second optical slit of the laser beam sensor to generate a second electrical pulse, picking up the scan laser beam, at a third position, using a third optical slit of the laser beam sensor to generate a third electrical pulse, and determining a spot size and a position of the laser beam based on the first to third electrical pulses.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: November 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Russell Budd, Robert Polastre, Paul Andry
  • Publication number: 20110290402
    Abstract: A method for attaching a handler to a wafer, the wafer comprising an integrated circuit (IC), includes forming a layer of an adhesive on the wafer, the adhesive comprising a polyimide-based polymer configured to withstand processing at a temperature of over about 280° C.; and adhering a handler to the wafer using the layer of adhesive. A system for attaching a handler to a wafer, the wafer comprising IC, includes a layer of an adhesive located on the wafer, the adhesive comprising a polyimide-based polymer configured to withstand processing at a temperature of over about 280° C.; and a handler adhered to the wafer using the layer of adhesive.
    Type: Application
    Filed: May 27, 2010
    Publication date: December 1, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Paul Andry, Bing Dang, John Knickerbocker, Aparna Prabhakar, Peter Sorce, Robert E. Trzcinski, Cornelia K. Tsang
  • Patent number: 7443246
    Abstract: A constant current bias approach that receives an input bias voltage and maintains a temperature independent constant current bias in a linear amplifier device. Integrated sense circuitry protects against unacceptable input voltages to guarantee bias stability. Fabrication in multiple semiconductor technologies and assembly into a single package allows for optimum cost and performance of DC bias and RF amplifier sections.
    Type: Grant
    Filed: October 21, 2003
    Date of Patent: October 28, 2008
    Assignee: Skyworks Solutions, Inc.
    Inventors: Paul Andrys, Mark Bloom, Hugh J. Finlay, David Ripley, Terry Shie, Kevin Hoheisel
  • Publication number: 20080036084
    Abstract: A laser release and glass chip removal process for a integrated circuit module avoiding carrier edge cracking is provided.
    Type: Application
    Filed: January 30, 2006
    Publication date: February 14, 2008
    Applicant: International Business Machines Corporation
    Inventors: Leena Buchwalter, Paul Andry, Matthew Farinelli, Sherif Goma, Raymond Horton, Edmund Sprogis
  • Publication number: 20080007341
    Abstract: According to an exemplary embodiment, an amplification module includes a power amplifier configured to receive an RF input signal and provide an RF output signal. The amplification module further includes an autobias control circuit configured to receive and convert the RF output signal to a control signal. The control signal can cause the power amplifier to have a quiescent current that increases substantially linearly in response to an increase in the RF output power of the RF output signal. The autobias control circuit can include a peak detector/log converter circuit coupled to a first input of a differential amplifier, where the differential amplifier outputs the control signal. The autobias control circuit can further include a DC reference circuit coupled to a second input of the differential amplifier. The amplification module further includes an analog bias circuit coupling the control voltage to a bias input of said power amplifier.
    Type: Application
    Filed: September 21, 2007
    Publication date: January 10, 2008
    Inventors: David Ripley, Paul Andrys, Keith Nellis
  • Publication number: 20070222065
    Abstract: An electronic dive and method of fabricating an electronic device. The method including placing a placement guide over a top surface of a module substrate, the placement guide having a guide opening, the guide opening extending from a top surface of the placement guide to a bottom surface of the placement guide; aligning the placement guide to an integrated circuit chip position on the module substrate; fixing the placement guide to the module substrate; placing an integrated circuit chip in the guide opening, sidewalls of the placement guide opening constraining electrically conductive bonding structures on bottom surface of the integrated circuit chip to self-align to an electrically conductive module substrate contact pad on the top surface of the module substrate in the integrated circuit chip position; and bonding the bonding structures to the module substrate contact pads, the bonding structures and the module substrate contact pads in direct physical and electrical contact after the bonding.
    Type: Application
    Filed: March 21, 2006
    Publication date: September 27, 2007
    Applicant: International Business Machines Corporation
    Inventors: Paul Andry, Leena Buchwalter, Raymond Horton, John Knickerbocker, Cornelia Tsang, Steven Wright
  • Publication number: 20070210446
    Abstract: Apparatus and methods are provided for integrating microchannel cooling modules within high-density electronic modules (e.g., chip packages, system-on-a-package modules, etc.,) comprising multiple high-performance IC chips. Electronic modules are designed such that high-performance (high power) IC chips are disposed in close proximity to the integrated cooling module (or cooling plate) for effective heat extraction. Moreover, electronic modules which comprise large surface area silicon carriers with multiple chips face mounted thereon are designed such that integrated silicon cooling modules are rigidly bonded to the back surfaces of such chips to increase the structural integrity of the silicon carriers.
    Type: Application
    Filed: April 13, 2007
    Publication date: September 13, 2007
    Inventors: Paul Andry, Evan Colgan, Lawrence Mok, Chirag Patel, David Seeger
  • Publication number: 20070048896
    Abstract: Conductive through vias are formed in electronic devices and electronic device carrier, such as, a silicon chip carrier. An annulus cavity is etched into the silicon carrier from the top side of the carrier and the cavity is filled with insulating material to form an isolation collar around a silicon core region. An insulating layer with at least one wiring level, having a portion in contact with the silicon core region, is formed on the top side of the carrier. Silicon is removed from the back side of the carrier sufficient to expose the distal portion of the isolation collar. The core region is etched out to expose the portion of the wiring level in contact with the silicon core region to form an empty via. The via is filled with conductive material in contact with the exposed portion of the wiring level to form a conductive through via to the wiring level. A solder bump formed, for example, from low melt C4 solder, is formed on the conductive via exposed on the carrier back side.
    Type: Application
    Filed: August 30, 2005
    Publication date: March 1, 2007
    Applicant: International Business Machines Corporation
    Inventors: Paul Andry, Chirag Patel, Edmund Sprogis, Cornelia Tsang
  • Publication number: 20070045844
    Abstract: A structure and a method for forming the same. The structure includes an integrated circuit comprising N chip electric pads, wherein N is a positive integer, and wherein the N chip electric pads are electrically connected to a plurality of devices on the integrated circuit. The structure further includes N solder bumps corresponding to the N chip electric pads. A semiconductor interposing shield is sandwiched between the integrated circuit and the N solder bumps. The structure further includes N electric conductors (i) passing through the semiconductor interposing shield and (ii) electrically connecting the N solder bumps to the N chip electric pads.
    Type: Application
    Filed: August 24, 2005
    Publication date: March 1, 2007
    Inventors: Paul Andry, Cyril Cabral, Kenneth Rodbell, Robert Wisnieff
  • Publication number: 20070001766
    Abstract: According to an exemplary embodiment, an amplification module includes a power amplifier configured to receive an RF input signal and provide an RF output signal. The amplification module further includes an autobias control circuit configured to receive and convert the RF output signal to a control signal. The control signal can cause the power amplifier to have a quiescent current that increases substantially linearly in response to an increase in the RF output power of the RF output signal. The autobias control circuit can include a peak detector/log converter circuit coupled to a first input of a differential amplifier, where the differential amplifier outputs the control signal. The autobias control circuit can further include a DC reference circuit coupled to a second input of the differential amplifier. The amplification module further includes an analog bias circuit coupling the control voltage to a bias input of said power amplifier.
    Type: Application
    Filed: June 29, 2005
    Publication date: January 4, 2007
    Inventors: David Ripley, Paul Andrys, Keith Nellis
  • Publication number: 20060180924
    Abstract: Apparatus and methods are provided for integrating microchannel cooling modules within high-density electronic modules (e.g., chip packages, system-on-a-package modules, etc.,) comprising multiple high-performance IC chips. Electronic modules are designed such that high-performance (high power) IC chips are disposed in close proximity to the integrated cooling module (or cooling plate) for effective heat extraction. Moreover, electronic modules which comprise large surface area silicon carriers with multiple chips face mounted thereon are designed such that integrated silicon cooling modules are rigidly bonded to the back surfaces of such chips to increase the structural integrity of the silicon carriers.
    Type: Application
    Filed: March 30, 2006
    Publication date: August 17, 2006
    Inventors: Paul Andry, Evan Colgan
  • Publication number: 20060103011
    Abstract: Apparatus and methods are provided for integrating microchannel cooling modules within high-density electronic modules (e.g., chip packages, system-on-a-package modules, etc.,) comprising multiple high-performance IC chips. Electronic modules are designed such that high-performance (high power) IC chips are disposed in close proximity to the integrated cooling module (or cooling plate) for effective heat extraction. Moreover, electronic modules which comprise large surface area silicon carriers with multiple chips face mounted thereon are designed such that integrated silicon cooling modules are rigidly bonded to the back surfaces of such chips to increase the structural integrity of the silicon carriers.
    Type: Application
    Filed: November 12, 2004
    Publication date: May 18, 2006
    Inventors: Paul Andry, Evan Colgan, Lawrence Mok, Chirag Patel, David Seeger
  • Publication number: 20060027934
    Abstract: A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.
    Type: Application
    Filed: October 3, 2005
    Publication date: February 9, 2006
    Inventors: Daniel Edelstein, Paul Andry, Leena Buchwalter, Jon Casey, Sherif Goma, Raymond Horton, Gareth Hougham, Michael Lane, Xiao Liu, Chirag Patel, Edmund Sprogis, Michelle Steen, Brian Sundlof, Cornelia Tsang, George Walker, Yu-Ting Cheng, Kenneth Ocheltree, Robert Montoye
  • Publication number: 20050121768
    Abstract: A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.
    Type: Application
    Filed: December 5, 2003
    Publication date: June 9, 2005
    Applicant: International Business Machines Corporation
    Inventors: Daniel Edelstein, Paul Andry, Leena Buchwalter, Jon Casey, Sherif Goma, Raymond Horton, Gareth Hougham, Michael Lane, Xiao Liu, Chirag Patel, Edmund Sprogis, Michelle Steen, Brian Sundlof, Cornelia Tsang, George Walker
  • Publication number: 20050106834
    Abstract: A method for filling vias, and in particular initially blind vias, in a wafer, and various apparatus for performing the method, comprising evacuating air from the vias; trapping at least a portion of the wafer and a paste for filling the vias between two surfaces; and pressurizing the paste to fill the vias.
    Type: Application
    Filed: November 3, 2003
    Publication date: May 19, 2005
    Inventors: Paul Andry, Jon Casey, Raymond Horton, Chiraq Patel, Edmund Sprogis, Brian Sundlof
  • Publication number: 20050082676
    Abstract: This disclosure teaches a method of filling deep vias or capping deep conducting paste filled vias in silicon or glass substrate using laser assisted chemical vapor deposition of metals. This method uses a continuous wave or pulsed laser to heat the via bottom and the growing metal fill selectively by selecting the laser wavelength such that silicon and/or glass do not absorb the energy of the laser in any appreciable manner to cause deposition in the field. Alternatively holographic mask or an array of micro lenses may be used to focus the laser beams to the vias to fill them with metal. The substrate is moved in a controlled manner in the z-direction away from the laser at about the rate of deposition thus causing the laser heating to be focused on the surface region of the growing metal fill.
    Type: Application
    Filed: October 17, 2003
    Publication date: April 21, 2005
    Applicant: International Business Machines Corporation
    Inventors: Paul Andry, Leena Buchwalter, Russell Budd, Thomas Wassick
  • Patent number: 6842067
    Abstract: An improved integrated bias reference provides a temperature and supply stable bias for devices such as radio frequency amplifiers with less complexity and expense than conventional bias references. The bias reference may be integrated onto a single GaAs die with other active circuitry such as an amplifier.
    Type: Grant
    Filed: April 30, 2002
    Date of Patent: January 11, 2005
    Assignee: Skyworks Solutions, Inc.
    Inventors: Paul Andrys, David Ripley
  • Publication number: 20040164805
    Abstract: A constant current bias approach that receives an input bias voltage and maintains a temperature independent constant current bias in a linear amplifier device. Integrated sense circuitry protects against unacceptable input voltages to guarantee bias stability. Fabrication in multiple semiconductor technologies and assembly into a single package allows for optimum cost and performance of DC bias and RF amplifier sections.
    Type: Application
    Filed: October 21, 2003
    Publication date: August 26, 2004
    Inventors: Paul Andrys, Mark Bloom, Hugh J. Finlay, David Ripley, Terry Shie, Kevin Hoheisel
  • Patent number: 6768382
    Abstract: In one exemplary embodiment, a sensing circuit for sensing an output power of a power amplifier comprises a biasing circuit coupled to a detection circuit. The biasing circuit feeds a base current to the power amplifier, and the detection circuit draws a mirror current of the base current. The mirror current is fed at a first node to each of an impedance circuit and a first FET, wherein a sense voltage is generated at the first node. In one exemplary embodiment, the first FET is activated when a beta parameter of the power amplifier decreases.
    Type: Grant
    Filed: March 28, 2003
    Date of Patent: July 27, 2004
    Assignee: Skyworks Solutions, Inc.
    Inventors: Terry Shie, Russ Wyse, David Ripley, Paul Andrys