Patents by Inventor Paul Andrys
Paul Andrys has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10166632Abstract: A method for aligning a scan laser beam on a wafer include scanning a scan laser beam across a laser beam sensor along a scan line, picking up a scan laser beam, at a first position, using a first optical slit of the laser beam sensor to generate a first electrical pulse, picking up the scan laser beam, at a second position, using a second optical slit of the laser beam sensor to generate a second electrical pulse, picking up the scan laser beam, at a third position, using a third optical slit of the laser beam sensor to generate a third electrical pulse, and determining a spot size and a position of the laser beam based on the first to third electrical pulses.Type: GrantFiled: November 22, 2017Date of Patent: January 1, 2019Assignee: International Business Machines CorporationInventors: Russell Budd, Robert Polastre, Paul Andry
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Patent number: 10118250Abstract: A method and system for aligning a scan laser beam on a wafer include scanning a scan laser beam across a laser beam sensor along a scan line, picking up a scan laser beam, at a first position, using a first optical slit of the laser beam sensor to generate a first electrical pulse, picking up the scan laser beam, at a second position, using a second optical slit of the laser beam sensor to generate a second electrical pulse, picking up the scan laser beam, at a third position, using a third optical slit of the laser beam sensor to generate a third electrical pulse, and determining a spot size and a position of the laser beam based on the first to third electrical pulses.Type: GrantFiled: September 15, 2017Date of Patent: November 6, 2018Assignee: International Business Machines CorporationInventors: Russell Budd, Robert Polastre, Paul Andry
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Publication number: 20110290402Abstract: A method for attaching a handler to a wafer, the wafer comprising an integrated circuit (IC), includes forming a layer of an adhesive on the wafer, the adhesive comprising a polyimide-based polymer configured to withstand processing at a temperature of over about 280° C.; and adhering a handler to the wafer using the layer of adhesive. A system for attaching a handler to a wafer, the wafer comprising IC, includes a layer of an adhesive located on the wafer, the adhesive comprising a polyimide-based polymer configured to withstand processing at a temperature of over about 280° C.; and a handler adhered to the wafer using the layer of adhesive.Type: ApplicationFiled: May 27, 2010Publication date: December 1, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Paul Andry, Bing Dang, John Knickerbocker, Aparna Prabhakar, Peter Sorce, Robert E. Trzcinski, Cornelia K. Tsang
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Patent number: 7443246Abstract: A constant current bias approach that receives an input bias voltage and maintains a temperature independent constant current bias in a linear amplifier device. Integrated sense circuitry protects against unacceptable input voltages to guarantee bias stability. Fabrication in multiple semiconductor technologies and assembly into a single package allows for optimum cost and performance of DC bias and RF amplifier sections.Type: GrantFiled: October 21, 2003Date of Patent: October 28, 2008Assignee: Skyworks Solutions, Inc.Inventors: Paul Andrys, Mark Bloom, Hugh J. Finlay, David Ripley, Terry Shie, Kevin Hoheisel
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Publication number: 20080036084Abstract: A laser release and glass chip removal process for a integrated circuit module avoiding carrier edge cracking is provided.Type: ApplicationFiled: January 30, 2006Publication date: February 14, 2008Applicant: International Business Machines CorporationInventors: Leena Buchwalter, Paul Andry, Matthew Farinelli, Sherif Goma, Raymond Horton, Edmund Sprogis
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Publication number: 20080007341Abstract: According to an exemplary embodiment, an amplification module includes a power amplifier configured to receive an RF input signal and provide an RF output signal. The amplification module further includes an autobias control circuit configured to receive and convert the RF output signal to a control signal. The control signal can cause the power amplifier to have a quiescent current that increases substantially linearly in response to an increase in the RF output power of the RF output signal. The autobias control circuit can include a peak detector/log converter circuit coupled to a first input of a differential amplifier, where the differential amplifier outputs the control signal. The autobias control circuit can further include a DC reference circuit coupled to a second input of the differential amplifier. The amplification module further includes an analog bias circuit coupling the control voltage to a bias input of said power amplifier.Type: ApplicationFiled: September 21, 2007Publication date: January 10, 2008Inventors: David Ripley, Paul Andrys, Keith Nellis
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Publication number: 20070222065Abstract: An electronic dive and method of fabricating an electronic device. The method including placing a placement guide over a top surface of a module substrate, the placement guide having a guide opening, the guide opening extending from a top surface of the placement guide to a bottom surface of the placement guide; aligning the placement guide to an integrated circuit chip position on the module substrate; fixing the placement guide to the module substrate; placing an integrated circuit chip in the guide opening, sidewalls of the placement guide opening constraining electrically conductive bonding structures on bottom surface of the integrated circuit chip to self-align to an electrically conductive module substrate contact pad on the top surface of the module substrate in the integrated circuit chip position; and bonding the bonding structures to the module substrate contact pads, the bonding structures and the module substrate contact pads in direct physical and electrical contact after the bonding.Type: ApplicationFiled: March 21, 2006Publication date: September 27, 2007Applicant: International Business Machines CorporationInventors: Paul Andry, Leena Buchwalter, Raymond Horton, John Knickerbocker, Cornelia Tsang, Steven Wright
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Publication number: 20070210446Abstract: Apparatus and methods are provided for integrating microchannel cooling modules within high-density electronic modules (e.g., chip packages, system-on-a-package modules, etc.,) comprising multiple high-performance IC chips. Electronic modules are designed such that high-performance (high power) IC chips are disposed in close proximity to the integrated cooling module (or cooling plate) for effective heat extraction. Moreover, electronic modules which comprise large surface area silicon carriers with multiple chips face mounted thereon are designed such that integrated silicon cooling modules are rigidly bonded to the back surfaces of such chips to increase the structural integrity of the silicon carriers.Type: ApplicationFiled: April 13, 2007Publication date: September 13, 2007Inventors: Paul Andry, Evan Colgan, Lawrence Mok, Chirag Patel, David Seeger
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Publication number: 20070045844Abstract: A structure and a method for forming the same. The structure includes an integrated circuit comprising N chip electric pads, wherein N is a positive integer, and wherein the N chip electric pads are electrically connected to a plurality of devices on the integrated circuit. The structure further includes N solder bumps corresponding to the N chip electric pads. A semiconductor interposing shield is sandwiched between the integrated circuit and the N solder bumps. The structure further includes N electric conductors (i) passing through the semiconductor interposing shield and (ii) electrically connecting the N solder bumps to the N chip electric pads.Type: ApplicationFiled: August 24, 2005Publication date: March 1, 2007Inventors: Paul Andry, Cyril Cabral, Kenneth Rodbell, Robert Wisnieff
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Publication number: 20070048896Abstract: Conductive through vias are formed in electronic devices and electronic device carrier, such as, a silicon chip carrier. An annulus cavity is etched into the silicon carrier from the top side of the carrier and the cavity is filled with insulating material to form an isolation collar around a silicon core region. An insulating layer with at least one wiring level, having a portion in contact with the silicon core region, is formed on the top side of the carrier. Silicon is removed from the back side of the carrier sufficient to expose the distal portion of the isolation collar. The core region is etched out to expose the portion of the wiring level in contact with the silicon core region to form an empty via. The via is filled with conductive material in contact with the exposed portion of the wiring level to form a conductive through via to the wiring level. A solder bump formed, for example, from low melt C4 solder, is formed on the conductive via exposed on the carrier back side.Type: ApplicationFiled: August 30, 2005Publication date: March 1, 2007Applicant: International Business Machines CorporationInventors: Paul Andry, Chirag Patel, Edmund Sprogis, Cornelia Tsang
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Publication number: 20070001766Abstract: According to an exemplary embodiment, an amplification module includes a power amplifier configured to receive an RF input signal and provide an RF output signal. The amplification module further includes an autobias control circuit configured to receive and convert the RF output signal to a control signal. The control signal can cause the power amplifier to have a quiescent current that increases substantially linearly in response to an increase in the RF output power of the RF output signal. The autobias control circuit can include a peak detector/log converter circuit coupled to a first input of a differential amplifier, where the differential amplifier outputs the control signal. The autobias control circuit can further include a DC reference circuit coupled to a second input of the differential amplifier. The amplification module further includes an analog bias circuit coupling the control voltage to a bias input of said power amplifier.Type: ApplicationFiled: June 29, 2005Publication date: January 4, 2007Inventors: David Ripley, Paul Andrys, Keith Nellis
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Publication number: 20060180924Abstract: Apparatus and methods are provided for integrating microchannel cooling modules within high-density electronic modules (e.g., chip packages, system-on-a-package modules, etc.,) comprising multiple high-performance IC chips. Electronic modules are designed such that high-performance (high power) IC chips are disposed in close proximity to the integrated cooling module (or cooling plate) for effective heat extraction. Moreover, electronic modules which comprise large surface area silicon carriers with multiple chips face mounted thereon are designed such that integrated silicon cooling modules are rigidly bonded to the back surfaces of such chips to increase the structural integrity of the silicon carriers.Type: ApplicationFiled: March 30, 2006Publication date: August 17, 2006Inventors: Paul Andry, Evan Colgan
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Publication number: 20060103011Abstract: Apparatus and methods are provided for integrating microchannel cooling modules within high-density electronic modules (e.g., chip packages, system-on-a-package modules, etc.,) comprising multiple high-performance IC chips. Electronic modules are designed such that high-performance (high power) IC chips are disposed in close proximity to the integrated cooling module (or cooling plate) for effective heat extraction. Moreover, electronic modules which comprise large surface area silicon carriers with multiple chips face mounted thereon are designed such that integrated silicon cooling modules are rigidly bonded to the back surfaces of such chips to increase the structural integrity of the silicon carriers.Type: ApplicationFiled: November 12, 2004Publication date: May 18, 2006Inventors: Paul Andry, Evan Colgan, Lawrence Mok, Chirag Patel, David Seeger
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Publication number: 20060027934Abstract: A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.Type: ApplicationFiled: October 3, 2005Publication date: February 9, 2006Inventors: Daniel Edelstein, Paul Andry, Leena Buchwalter, Jon Casey, Sherif Goma, Raymond Horton, Gareth Hougham, Michael Lane, Xiao Liu, Chirag Patel, Edmund Sprogis, Michelle Steen, Brian Sundlof, Cornelia Tsang, George Walker, Yu-Ting Cheng, Kenneth Ocheltree, Robert Montoye
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Publication number: 20050121768Abstract: A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.Type: ApplicationFiled: December 5, 2003Publication date: June 9, 2005Applicant: International Business Machines CorporationInventors: Daniel Edelstein, Paul Andry, Leena Buchwalter, Jon Casey, Sherif Goma, Raymond Horton, Gareth Hougham, Michael Lane, Xiao Liu, Chirag Patel, Edmund Sprogis, Michelle Steen, Brian Sundlof, Cornelia Tsang, George Walker
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Publication number: 20050106834Abstract: A method for filling vias, and in particular initially blind vias, in a wafer, and various apparatus for performing the method, comprising evacuating air from the vias; trapping at least a portion of the wafer and a paste for filling the vias between two surfaces; and pressurizing the paste to fill the vias.Type: ApplicationFiled: November 3, 2003Publication date: May 19, 2005Inventors: Paul Andry, Jon Casey, Raymond Horton, Chiraq Patel, Edmund Sprogis, Brian Sundlof
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Publication number: 20050082676Abstract: This disclosure teaches a method of filling deep vias or capping deep conducting paste filled vias in silicon or glass substrate using laser assisted chemical vapor deposition of metals. This method uses a continuous wave or pulsed laser to heat the via bottom and the growing metal fill selectively by selecting the laser wavelength such that silicon and/or glass do not absorb the energy of the laser in any appreciable manner to cause deposition in the field. Alternatively holographic mask or an array of micro lenses may be used to focus the laser beams to the vias to fill them with metal. The substrate is moved in a controlled manner in the z-direction away from the laser at about the rate of deposition thus causing the laser heating to be focused on the surface region of the growing metal fill.Type: ApplicationFiled: October 17, 2003Publication date: April 21, 2005Applicant: International Business Machines CorporationInventors: Paul Andry, Leena Buchwalter, Russell Budd, Thomas Wassick
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Patent number: 6842067Abstract: An improved integrated bias reference provides a temperature and supply stable bias for devices such as radio frequency amplifiers with less complexity and expense than conventional bias references. The bias reference may be integrated onto a single GaAs die with other active circuitry such as an amplifier.Type: GrantFiled: April 30, 2002Date of Patent: January 11, 2005Assignee: Skyworks Solutions, Inc.Inventors: Paul Andrys, David Ripley
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Publication number: 20040164805Abstract: A constant current bias approach that receives an input bias voltage and maintains a temperature independent constant current bias in a linear amplifier device. Integrated sense circuitry protects against unacceptable input voltages to guarantee bias stability. Fabrication in multiple semiconductor technologies and assembly into a single package allows for optimum cost and performance of DC bias and RF amplifier sections.Type: ApplicationFiled: October 21, 2003Publication date: August 26, 2004Inventors: Paul Andrys, Mark Bloom, Hugh J. Finlay, David Ripley, Terry Shie, Kevin Hoheisel
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Patent number: 6768382Abstract: In one exemplary embodiment, a sensing circuit for sensing an output power of a power amplifier comprises a biasing circuit coupled to a detection circuit. The biasing circuit feeds a base current to the power amplifier, and the detection circuit draws a mirror current of the base current. The mirror current is fed at a first node to each of an impedance circuit and a first FET, wherein a sense voltage is generated at the first node. In one exemplary embodiment, the first FET is activated when a beta parameter of the power amplifier decreases.Type: GrantFiled: March 28, 2003Date of Patent: July 27, 2004Assignee: Skyworks Solutions, Inc.Inventors: Terry Shie, Russ Wyse, David Ripley, Paul Andrys