Abstract: Programming field programmable gate array (FPGA) digital electronic integrated circuits (ICs) or other ICs that support partial reconfiguration, a particular FPGA having reconfigurable partitions and primitive variations configurable in each of the reconfigurable partitions, comprises: before writing configuration bitstreams to the FPGA, compiling and storing primitive bitstreams for different primitive functions that can be implemented on the particular FPGA; receiving input in a graphical user interface to connect graphical blocks representing functional logic of an algorithm to implement on the particular FPGA, the graphical blocks relating to reconfigurable logic; automatically determining a subset of the primitive functions comprising particular primitive functions that correspond to the graphical blocks; obtaining, from the digital storage, a subset of the primitive bitstreams that corresponds to the subset of the primitive functions; using partial reconfiguration operations, writing the subset of the p

Abstract: Programming field programmable gate array (FPGA) digital electronic integrated circuits (ICs) or other ICs that support partial reconfiguration, a particular FPGA having reconfigurable partitions and primitive variations configurable in each of the reconfigurable partitions, comprises: before writing configuration bitstreams to the FPGA, compiling and storing primitive bitstreams for different primitive functions that can be implemented on the particular FPGA; receiving input in a graphical user interface to connect graphical blocks representing functional logic of an algorithm to implement on the particular FPGA, the graphical blocks relating to reconfigurable logic; automatically determining a subset of the primitive functions comprising particular primitive functions that correspond to the graphical blocks; obtaining, from the digital storage, a subset of the primitive bitstreams that corresponds to the subset of the primitive functions; using partial reconfiguration operations, writing the subset of the p

Abstract: The present disclosure relates to blended analog-to-digital conversion for digital test and measurement devices. A first analog-to-digital converter (ADC) converts an analog signal into a first digital signal a first sampling rate. A digital filtering component generates a filtered digital signal by processing the first digital signal. An analog low pass filter filters the analog signal to generate a filtered analog signal. A second ADC converts the filtered analog signal into a second digital signal. A digital subtractor circuit subtracts the filtered digital signal from the first digital signal or the second digital signal. A digital adder circuit generates a blended digital signal by processing an output of the digital subtractor circuit and one of the first digital signal or the second digital signal.

Abstract: Systems and methods are provided for blended analog-to-digital conversion for digital test and measurement devices. A first-frequency-domain circuit path is configured to generate a first processed digital signal having high fidelity to an analog signal over a first frequency domain. A second-frequency-domain circuit path is configured to generate a second processed digital signal having high fidelity to the analog signal over a second frequency domain. A blended digital signal is generated using the first processed digital signal and the second processed digital signal. The blended digital signal can have high fidelity to the analog signal over multiple frequency domains.

Abstract: In an embodiment, a method is disclosed providing an improvement in speed and efficiency of programming field programmable gate array (FPGA) digital electronic integrated circuits (ICs) or other ICs that support partial reconfiguration, a particular FPGA having a plurality of reconfigurable partitions and a plurality of primitive variations configurable in each of the reconfigurable partitions, the method comprising: before writing configuration bitstreams to the particular FPGA, compiling and storing, using digital storage, a plurality of primitive bitstreams for a plurality of different primitive functions that can be written to and implemented on the particular FPGA; receiving input in a graphical user interface to select and connect graphical blocks representing functional logic of an algorithm to implement on the particular FPGA, the graphical blocks relating to reconfigurable logic; automatically determining a subset of the primitive functions comprising particular primitive functions that correspond to