Patents by Inventor Paul Anthony Winser

Paul Anthony Winser has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatus for use in a computer systems
    Patent number: 7346722
    Abstract: Apparatus for use in a computer system comprises a bus architecture, a plurality of modules connected to the bus architecture, at least one module being latency tolerant and at least one module being latency intolerant. The bus architecture comprises a primary bus (3) having latency intolerant modules connected thereto, a secondary bus (4) having latency tolerant modules connected thereto, and a primary to secondary bus interface module (5) interconnecting the primary and secondary buses.
    Type: Grant
    Filed: April 20, 2004
    Date of Patent: March 18, 2008
    Assignee: ClearSpeed Technology plc
    Inventors: Richard Carl Phelps, Paul Anthony Winser
  • Apparatus for use in a computer system
    Patent number: 7054969
    Abstract: Apparatus for use in a computer system comprises a bus architecture, a plurality of modules connected to the bus architecture, at least one module being latency tolerant and at least one module being latency intolerant. The bus architecture comprises a primary bus (3) having latency intolerant modules connected thereto, a secondary bus (4) having latency tolerant modules connected thereto, and a primary to secondary bus interface module (5) interconnecting the primary and secondary buses.
    Type: Grant
    Filed: September 16, 1999
    Date of Patent: May 30, 2006
    Assignee: ClearSpeed Technology plc
    Inventors: Richard Carl Phelps, Paul Anthony Winser
  • Apparatus for use in a computer systems
    Publication number: 20040199705
    Abstract: Apparatus for use in a computer system comprises a bus architecture, a plurality of modules connected to the bus architecture, at least one module being latency tolerant and at least one module being latency intolerant. The bus architecture comprises a primary bus (3) having latency intolerant modules connected thereto, a secondary bus (4) having latency tolerant modules connected thereto, and a primary to secondary bus interface module (5) interconnecting the primary and secondary buses.
    Type: Application
    Filed: April 20, 2004
    Publication date: October 7, 2004
    Inventors: Richard Carl Phelps, Paul Anthony Winser
  • Apparatus for use in a computer systems
    Publication number: 20040199706
    Abstract: Apparatus for use in a computer system comprises a bus architecture, a plurality of modules connected to the bus architecture, at least one module being latency tolerant and at least one module being latency intolerant. The bus architecture comprises a primary bus (3) having latency intolerant modules connected thereto, a secondary bus (4) having latency tolerant modules connected thereto, and a primary to secondary bus interface module (5) interconnecting the primary and secondary buses.
    Type: Application
    Filed: April 20, 2004
    Publication date: October 7, 2004
    Inventors: Richard Carl Phelps, Paul Anthony Winser
  • Apparatus for use in a computer systems
    Publication number: 20040199692
    Abstract: Apparatus for use in a computer system comprises a bus architecture, a plurality of modules connected to the bus architecture, at least one module being latency tolerant and at least one module being latency intolerant. The bus architecture comprises a primary bus (3) having latency intolerant modules connected thereto, a secondary bus (4) having latency tolerant modules connected thereto, and a primary to secondary bus interface module (5) interconnecting the primary and secondary buses.
    Type: Application
    Filed: April 20, 2004
    Publication date: October 7, 2004
    Inventors: Richard Carl Phelps, Paul Anthony Winser
  • Apparatus for use in a computer system
    Publication number: 20040199704
    Abstract: Apparatus for use in a computer system comprises a bus architecture, a plurality of modules connected to the bus architecture, at least one module being latency tolerant and at least one module being latency intolerant. The bus architecture comprises a primary bus (3) having latency intolerant modules connected thereto, a secondary bus (4) having latency tolerant modules connected thereto, and a primary to secondary bus interface module (5) interconnecting the primary and secondary buses.
    Type: Application
    Filed: April 20, 2004
    Publication date: October 7, 2004
    Inventors: Richard Carl Phelps, Paul Anthony Winser