Abstract: A semiconductor device comprising a drain region, a body region overlying the drain region and defining an upper surface, source regions extending from adjacent the upper surface of the body region towards the drain region, and a series of indentations extending into and through the body region such that lower side walls of each indentation are defined by portions of the body and drain regions and upper side walls of each indentation are defined by the source region. A lower portion of each indentation is filled with a gate region isolated from the side walls by a first insulating layer and covered by a second insulating layer. A source conductor overlies the upper surface and is electrically connected to the source regions, and a gate conductor is electrically connected to each gate region. The source conductor extends into all upper portion of each indentation to contact portions of the upper side Walls of the indentation which are defined by the source regions.

Abstract: A method of semiconductor device fabrication comprising forming at least the indentation in a surface of a semiconductor body. The indentation is partially filled with a filler material such that walls of the indentation are exposed above an upper surface of the filler material. First and second dopants are introduced through the exposed walls of the indentation and first and second doped regions formed. The first doped region extends into the semiconductor body around the filled portion of the indentation to a first region boundary which is at a predetermined first depth relative to the upper surface of the filler material. The second doped region extends into the semiconductor body around the filled portion of the indentation to a second region boundary which is at a predetermined second depth relative to the upper surface of the filler material.