Patents by Inventor Paul Armand Calo

Paul Armand Calo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230230903
    Abstract: A semiconductor chip is provided. The semiconductor chip may include a front side including a control chip contact and a first controlled chip contact, a back side including a second controlled chip contact, a backside metallization formed over the back side in contact with the second controlled chip contact, and a stop region extending at least partially along an outer edge of the back side between a contact portion of the backside metallization and the outer edge of the back side. The contact portion is configured to be attached to an electrically conductive structure by a die attach material, a surface of the stop region is recessed with respect to a surface of the contact portion, and/or the surface of the stop region has a lower wettability with respect to the die attach material than the contact portion.
    Type: Application
    Filed: December 21, 2022
    Publication date: July 20, 2023
    Applicant: Infineon Technologies AG
    Inventors: Hooi Boon TEOH, Hao ZHUANG, Oliver BLANK, Paul Armand CALO, Markus DINKEL, Josef Höglauer, Daniel Hölzl, Wee Aun JASON LIM, Gerhard Thomas Nöbauer, Ralf OTREMBA, Martin Pölzl, Ying Pok SAM, Xaver Schlögel, Chee Voon TAN
  • Publication number: 20230095545
    Abstract: A semiconductor package includes a leadframe including a diepad and a first row of leads, wherein at least one lead of the first row of leads is physically separated from the diepad by a gap. The semiconductor package further includes a semiconductor component arranged on the leadframe. The semiconductor package further includes an encapsulation material encapsulating the leadframe and the semiconductor component, wherein the encapsulation material includes a bottom surface arranged at a bottom surface of the semiconductor package, a top surface and a side surface extending from the bottom surface to the top surface. A side surface of at least one lead of the first row of leads is flush with the side surface of the encapsulation material. The flush side surface of the at least one lead is covered by an electroplated metal coating.
    Type: Application
    Filed: September 22, 2022
    Publication date: March 30, 2023
    Inventors: Paul Armand Calo, Thomas Bemmerl, Joo Ming Goa, Edward Myers, Wee Boon Tay, Stefan Macheiner, Markus Dinkel, Andreas Piller
  • Patent number: 9640459
    Abstract: A semiconductor device includes a leadframe and a semiconductor chip including a contact. The contact faces the leadframe and is electrically coupled to the leadframe via solder. The semiconductor device includes a solder barrier adjacent to the first contact and an edge of the chip.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: May 2, 2017
    Assignee: Infineon Technologies AG
    Inventors: Wee Boon Tay, Kuan Ching Woo, Paul Armand Calo
  • Patent number: 8497164
    Abstract: A semiconductor die package. The semiconductor die package includes a premolded clip structure assembly having a clip structure, a semiconductor die attached to the clip structure, and a first molding material covering at least a portion of the clip structure and the semiconductor die. The semiconductor die package also includes a leadframe structure having a die attach pad, where the leadframe structure is attached to premolded clip structure assembly.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: July 30, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Armand Vincent C. Jereza, Paul Armand Calo, Erwin Victor R. Cruz
  • Publication number: 20120329214
    Abstract: A semiconductor die package. The semiconductor die package includes a premolded clip structure assembly having a clip structure, a semiconductor die attached to the clip structure, and a first molding material covering at least a portion of the clip structure and the semiconductor die. The semiconductor die package also includes a leadframe structure having a die attach pad, where the leadframe structure is attached to premolded clip structure assembly.
    Type: Application
    Filed: July 13, 2012
    Publication date: December 27, 2012
    Inventors: Armand Vincent C. Jereza, Paul Armand Calo, Erwin Victor R. Cruz
  • Patent number: 8222718
    Abstract: A semiconductor die package. The semiconductor die package includes a premolded clip structure assembly having a clip structure, a semiconductor die attached to the clip structure, and a first molding material covering at least a portion of the clip structure and the semiconductor die. The semiconductor die package also includes a leadframe structure having a die attach pad, where the leadframe structure is attached to premolded clip structure assembly.
    Type: Grant
    Filed: February 5, 2009
    Date of Patent: July 17, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Armand Vincent C. Jereza, Paul Armand Calo, Erwin Victor R. Cruz
  • Patent number: 8110492
    Abstract: Disclosed in this specification is a semiconductor package with a die attach pad and a lead frame which are electrically and mechanically connected to one another through a conductive wire ribbon. Such a configuration reduces the package footprint and also permits different styles of die attach pads and lead frames to be interchanged, thus reducing production costs.
    Type: Grant
    Filed: August 13, 2010
    Date of Patent: February 7, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Erwin Ian V. Almagro, Honorio T. Granada, Jr., Paul Armand Calo
  • Publication number: 20100304534
    Abstract: Disclosed in this specification is a semiconductor package with a die attach pad and a lead frame which are electrically and mechanically connected to one another through a conductive wire ribbon. Such a configuration reduces the package footprint and also permits different styles of die attach pads and lead frames to be interchanged, thus reducing production costs.
    Type: Application
    Filed: August 13, 2010
    Publication date: December 2, 2010
    Inventors: Erwin Ian V. Almagro, Honorio T. Granada, JR., Paul Armand Calo
  • Patent number: 7800207
    Abstract: Disclosed in this specification is a semiconductor package with a die attach pad and a lead frame which are electrically and mechanically connected to one another through a conductive wire ribbon. Such a configuration reduces the package footprint and also permits different styles of die attach pads and lead frames to be interchanged, thus reducing production costs.
    Type: Grant
    Filed: October 17, 2007
    Date of Patent: September 21, 2010
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Erwin Ian V. Almagro, Honorio T. Granada, Jr., Paul Armand Calo
  • Publication number: 20100193921
    Abstract: A semiconductor die package. The semiconductor die package includes a premolded clip structure assembly having a clip structure, a semiconductor die attached to the clip structure, and a first molding material covering at least a portion of the clip structure and the semiconductor die. The semiconductor die package also includes a leadframe structure having a die attach pad, where the leadframe structure is attached to premolded clip structure assembly.
    Type: Application
    Filed: February 5, 2009
    Publication date: August 5, 2010
    Inventors: Armand Vincent C. Jereza, Paul Armand Calo, Erwin Victor R. Cruz
  • Patent number: 7586179
    Abstract: Disclosed in this specification is a wireless semiconductor package with multiple dies, at least two of which are attached to a thermally and electrically conductive heat sink. The package provides an efficient means for dissipating heat.
    Type: Grant
    Filed: October 9, 2007
    Date of Patent: September 8, 2009
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Paul Armand Calo, Margie T. Rios, Tiburcio A. Maldo, JoonSeo Son, Erwin Ian V. Almagro
  • Publication number: 20090102031
    Abstract: Disclosed in this specification is a semiconductor package with a die attach pad and a lead frame which are electrically and mechanically connected to one another through a conductive wire ribbon. Such a configuration reduces the package footprint and also permits different styles of die attach pads and lead frames to be interchanged, thus reducing production costs.
    Type: Application
    Filed: October 17, 2007
    Publication date: April 23, 2009
    Inventors: Erwin Ian V. Almagro, Honorio T. Granada, JR., Paul Armand Calo
  • Publication number: 20090091010
    Abstract: Disclosed in this specification is a wireless semiconductor package with multiple dies, at least two of which are attached to a thermally and electrically conductive heat sink. The package provides an efficient means for dissipating heat.
    Type: Application
    Filed: October 9, 2007
    Publication date: April 9, 2009
    Inventors: Paul Armand Calo, Margie T. Rios, Tiburcio A. Maldo, JoonSeo Son, Erwin Ian Almagro
  • Patent number: 7402462
    Abstract: A folded frame carrier has a die attach pad (DAP) 30 and one or more folded edges 32, 33, 34, 35. Each folded edge has one or more studs 36 and each stud has a trapezoidal tip. The folded frame carrier may be made of single gauge copper or copper alloy. Multiple folded frame carriers may be formed between opposite rails of a lead frame. The folded edges are cut with a relief groove. The tips are formed in edges of the DAP and then the tips are folded upright. The tips provide electrical connection to the terminal on the rear surface of a power semiconductor mounted on the DAP.
    Type: Grant
    Filed: July 12, 2005
    Date of Patent: July 22, 2008
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Ruben P. Madrid, Marvin Gestole, Erwin Victor R. Cruz, Romel N. Madatad, Arniel Jaud, Paul Armand Calo