Abstract: A digital PWM modulator modulates a digital input signal to drive a PWM signal to a PWM DAC susceptible to introducing inter-symbol interference (ISI) in small PWM edge separation presence causing audio THDN degradation. A multi-bit quantizer switches from a first to second mode when the input signal rises above a threshold. The quantizer quantizes the input signal into a quantized output signal, each sample of which has a code selected from respective first and second quantization code sets. The second set, relative to the first set, causes the digital PWM signal to have increased edge separation to reduce the ISI at high input levels. The first set includes small magnitude codes relative to the second set to reduce quantization noise at low input levels. The threshold is sufficiently low to cause the quantized output signal to be dominated by small codes when operating in the first mode.

Abstract: A digital PWM modulator modulates a digital input signal to drive a PWM signal to a PWM DAC susceptible to introducing inter-symbol interference (ISI) in small PWM edge separation presence causing audio THDN degradation. A multi-bit quantizer switches from a first to second mode when the input signal rises above a threshold. The quantizer quantizes the input signal into a quantized output signal, each sample of which has a code selected from respective first and second quantization code sets. The second set, relative to the first set, causes the digital PWM signal to have increased edge separation to reduce the ISI at high input levels. The first set includes small magnitude codes relative to the second set to reduce quantization noise at low input levels. The threshold is sufficiently low to cause the quantized output signal to be dominated by small codes when operating in the first mode.

Abstract: A class-D amplifier system includes one or more pulse width modulation (PWM) output paths at least one of which includes one or more digital closed-loop PWM modulators (DCL-PWMM) in which at least one of the DCL_PWMM includes a digital integrator that provides an output value and receives a feedback value. The output value has an output resolution and the feedback value has a feedback resolution that is coarser than the output resolution. The output value is the sum of an integer multiple of the feedback resolution and a residue. Control logic decreases/increases the residue of the digital integrator toward an integer multiple of the feedback resolution over a plurality of clock cycles in response to a request to transition the class-D amplifier and forces an output of the DCL_PWMM to have an approximate 50% duty cycle after decreasing/increasing the residue over the plurality of clock cycles.

Abstract: A receiver technique includes generating a DC offset compensation signal based on a frequency offset-compensated received signal and a frequency offset indication signal. The technique includes generating a DC offset-compensated received signal based on the DC offset compensation signal and a received signal. The frequency offset-compensated received signal may be generated using a first Coordinate Rotation DIgital Computer (CORDIC) responsive to the DC offset-compensated received symbol and the frequency offset indication signal. The DC offset compensation signal may be generated using a second CORDIC responsive to the frequency offset indication signal and a real-valued signal.

Abstract: A receiver technique includes generating a DC offset compensation signal based on a frequency offset-compensated received signal and a frequency offset indication signal. The technique includes generating a DC offset-compensated received signal based on the DC offset compensation signal and a received signal. The frequency offset-compensated received signal may be generated using a first Coordinate Rotation DIgital Computer (CORDIC) responsive to the DC offset-compensated received symbol and the frequency offset indication signal. The DC offset compensation signal may be generated using a second CORDIC responsive to the frequency offset indication signal and a real-valued signal.

Abstract: An encoded signal is modulated to produce a first radio frequency (RF) signal that is transmitted to a client module over a first transceiver channel when a first transceiver module is in a transceive mode. A channel scan is performed when the first transceiver module is in a scan mode. The encoded signal is modulated to produce a second RF signal and that is transmitted over a second transceiver channel when a second transceiver module is in a transceive mode.

Abstract: A method for field error checking begins by decoding a predetermined pattern of a field of a frame to produce a decoded pattern. The method continues by determining, for the decoded pattern, a path metric distance of a predetermined state of a plurality of states of the decoding. The method continues by comparing the path metric distance with an excepted path metric distance for the predetermined state. The method continues by indicating a field error when the path metric distance compares unfavorably with the excepted path metric distance.

Abstract: A method and apparatus for accurately detecting the presence of a valid signal includes processing that begins by determining the energy level of an input signal in real time to produce a real time energy level. The processing then continues by delaying the input by a period of the valid signal to produce a delayed input. The processing then continues by correlating the input with the delayed input to produce a correlated input. The processing continues by determining the energy of the correlated input to produce a correlated energy level. The processing then continues by comparing the correlated energy level with the real time energy level to produce a probability that the input is a valid signal. The processing then continues by generating a valid signal probability indication based on the probability that the input is a valid signal.

Abstract: A method and apparatus for adjusting symbol timing and/or symbol interval range of a receive burst of data within a radio receiver include processing that begins by receiving a radio frequency signal that includes bursts of data. The process then continues by determining a frequency offset for the burst of data based on a difference between the transmitter processing rate and a receiver processing rate The processing then continues by determining a symbol timing offset and/or a symbol interval range offset based on the frequency offset. The process then proceeds by adjusting the initial symbol positioning and/or the symbol interval range offset of a burst of data based on the symbol timing offset.

Abstract: A first direct current (DC) component of a first amplified representation of a received signal at an output of an amplifier set to a first gain setting is determined during a first expected idle period of a received signal. A second DC component of a second amplified representation of the received signal at the output of the amplifier set to the first gain setting is determined during a second expected idle period of the received signal. A first average DC component is determined based at least in part on the first and second DC components and a DC offset used by the amplifier when set to the first gain setting is adjusted based on a comparison of the first average DC component to one or more threshold values.

Abstract: A correlation module includes a plurality of first functional modules, a plurality of second functional modules, a plurality of function adjust modules, a summation module, a correlation value register, and a correlation evaluation module. The plurality of first functional modules is operably coupled to perform a first function upon a first corresponding pipelined data element to produce a first corresponding value. The plurality of second functional modules is operably coupled to perform a second function upon a second corresponding pipelined data element to produce a second corresponding value. The plurality of function adjust modules is operably coupled to selected ones of the plurality of first functional modules and to selected ones of the plurality of second functional modules. The summation module is operably coupled to sum the plurality of first corresponding values, the plurality of second corresponding values, and a previous correlation value to produce a current correlation value.

Abstract: A method for detecting validity of a received signal begins by performing an auto-correlation on the received signal to produce an auto-correlation resultant. The process continues by performing a cross-correlation on the receive signal with a reference signal to produce a cross-correlation resultant. The process then continues by mathematically relating the auto-correlation resultant with the cross-correlation resultant to produce a mathematical correlation relationship. The process then proceeds by interpreting the mathematical correlation relationship to indicate whether the receive signal is valid or not.

Abstract: A valid signal may be detected by initializing gain settings of the receiver section. The processing then continues by measuring received signal strength of a signal received by the receiver section to produce a 1st received signal strength indication (RSSI). The processing continues by adjusting the gain setting of the receiver section such that the 1st received signal strength indication is a predetermined offset less than a signal strength threshold. The process then continues by measuring the received signal strength of the gain adjusted representation of the signal to produce a 2nd received signal strength indication. The processing continues by appending a 2nd offset to the 2nd received signal strength value to produce an adjusted received signal strength indication value when the 2nd received signal strength value drifts from the signal strength threshold less the predetermined offset.

Abstract: A radio receiver includes a first diversity antenna structure, a second diversity antenna structure, a first RF receiver section, a second RF receiver section, a combining module, and a baseband processing module. The first diversity antenna structure includes a plurality of first antennas and each of the plurality of first antennas is operably coupled to receive inbound radio frequency (RF) signals, wherein the first diversity antenna structure provides the received inbound RF signals from one of the plurality of first antennas based on a first antenna selection signal to produce first received inbound RF signals. The second diversity antenna structure includes a plurality of second antennas and each of the plurality of second antennas is operably coupled to receive the inbound RF signals, wherein the second diversity antenna structure provides the received inbound RF signals from one of the plurality of second antennas based on a second antenna selection signal to produce second received inbound RF signals.

Abstract: A method and apparatus for accurately detecting the presence of a valid signal includes processing that begins by determining the energy level of an input signal in real time to produce a real time energy level. The processing then continues by delaying the input by a period of the valid signal to produce a delayed input. The processing then continues by correlating the input with the delayed input to produce a correlated input. The processing continues by determining the energy of the correlated input to produce a correlated energy level. The processing then continues by comparing the correlated energy level with the real time energy level to produce a probability that the input is a valid signal. The processing then continues by generating a valid signal probability indication based on the probability that the input is a valid signal.

Abstract: A data converter (10) and a method for attenuating noise in an output signal generated by the data converter (10). The data converter (10) includes a sigma-delta modulator (16), a digital-to-analog converter (17), a clock generator (19) connected to the digital-to-analog converter (17), and a clock control circuit (18) connected to the clock generator (19). The clock control circuit (18) enables or disables the clock generator (19) in accordance with the single-bit digital signal to cause a notch characteristic in the output signal for attenuating noise in the output signal.