Abstract: A device, includes an instruction buffer. The instruction buffer is configured to store instructions related to at least a portion of a data stream to be analyzed by a state machine engine as the device. The state machine engine includes configurable elements configured to analyze the at least a portion of a data stream and to selectively output the result of the analysis. Additionally, the instruction buffer is configured to receive the indications as part of a direct memory access (DMA) transfer.

Abstract: A processing apparatus for processing multiple video programs from one or more transport streams. The processing apparatus has a transport processing circuit that includes multiple transport processor units. The transport processor units utilize a common transport processor memory unit having demux context entries containing processing and hardware state information for packet types. Each transport processor unit includes a transport interface for identifying data packets to be acquired from the transport stream, a demultiplexing processor for processing the acquired data packets, and a demultiplexing DMA unit for memory handling operations of the processed data packets. Index chaining allows the transport processor units to access information from the transport processor memory unit. The method uses indices to access demux context entries from the transport processor memory unit. Related DMA indices are used to access memory handling information from the transport processor memory unit.

Abstract: A processing apparatus for processing multiple video programs from one or more transport streams. The processing apparatus has a transport processing circuit that includes multiple transport processor units. The transport processor units utilize a common transport processor memory unit having demux context entries containing processing and hardware state information for packet types. Each transport processor unit includes a transport interface for identifying data packets to be acquired from the transport stream, a demultiplexing processor for processing the acquired data packets, and a demultiplexing DMA unit for memory handling operations ofthe processed data packets. Index chaining allows the transport processor units to access information from the transport processor memory unit. The method uses indices to access demux context entries from the transport processor memory unit. Related DMA indices are used to access memory handling information from the transport processor memory unit.

Abstract: Each of a plurality of individually heated circularly located susceptors supports and heats one of a plurality of wafers within a processing chamber. An overhead gas dispersion head, vertically aligned with each susceptor, directs, in combination with downstream flow control structure, flow of a reactant gas radially uniformly across the supported wafer. A spider sequentially relocates each of the wafers, as a group, to an adjacent susceptor. Wafer handling apparatus replaces each processed wafer to provide a high production rate throughput. A source of RF energy radiating essentially primarily between each gas dispersion head and its associated susceptor provides a plasma enhanced environment and the low level intensity elsewhere within the reactor reduces residual deposits.

Abstract: A neural network is implemented by discrete-time, continuous voltage state analog device in which neuron, synapse and synaptic strength signals are generated in highly parallel analog circuits in successive states from stored values of the interdependent signals calculated in a previous state. The neuron and synapse signals are refined in a relaxation loop while the synaptic strength signals are held constant. In learning modes, the synaptic strength signals are modified in successive states from stable values of the analog neuron signals. The analog signals are stored for as long as required in master/slaver sample and hold circuits as digitized signals which are periodically refreshed to maintain the stored voltage within a voltage window bracketing the original analog signal.

Abstract: A state analog memory device for storing approximations of analog signals for prolonged periods of time converts the analog signal in an n-ary digitizer to the one of a plurality of a discrete levels which is the next greater in magnitude than the applied signal. This digitized signal is then serially stored in an analog storage element comprising connected master and slave sample and hold circuits by a two stage control signal. Periodically, at intervals shorter in duration than the time in which the stored signals would droop to the next lower n level, the stored signal is refreshed by feeding the signal stored in the slave sample and hold circuit back to the digitizer which boosts it back up to the one level which is reentered in the master/slave sample and hold circuits. A state analog dynamic RAM utilizes an array of the analog store elements and a plurality of n-ary digitizers for simultaneously refreshing rows of the storage elements at a time.