Abstract: A high speed data buffer array allocation circuit is provided in association with a plurality of buffer memories for directing high speed data into the memories. The circuitry employs high speed MOS technology to implement high speed switching and data allocation. The data packet input, generally from an uninterruptible source, is directed and written into a first available buffer memory. The memory can thereafter be read by a host computer. Flags are set indicating the availability of the memory for reading. The data buffer allocation circuit has a plurality of selection circuits connected in an ordered linear array for effectively passing therethrough to the circuit associated with the first available buffer, a data ready input signal. In response to the data ready input signal, the selection circuit and associated gating circuit provide the necessary control to direct the data to the associated memory and to thereafter leave a flag indicating the availability of data.

Abstract: A token-passing, ring-based data communications network provides a distributive method and apparatus for detecting and regenerating a lost token. The method includes, after detection of the loss of the token, transmitting at a detecting node a data packet not including a token, the data packet uniquely identifying the transmitting node as the data source. Simultaneously, the transmitting node, after transmitting the tokenless data packet, strips all incoming data from the network. If the transmitted packet is successfully received by the transmitting node, a new token is generated by the node. If the packet is not received, the node defers to an arbitration method which includes delaying a next data packet transmission for a probabilistically determined period of time. The mean time upon which the probabilistic approach is based increases with each unsuccessful data packet transmission attempt.

Abstract: An interface circuit including a FET inverter with its N channel device being part of the controlled leg of a first current mirror and its P channel device being part of the controlled leg of a second current mirror. The operating point of the inverter is the reference signal applied on the input to the current mirrors. The controlled leg of the first current mirror includes a variable current source responsive to the input signal and the controlled leg of the second current mirror includes a variable current sink for improving the response time of the inverter and compensates the inverter for manufacturing tolerances.

Abstract: An elliptical, interdigital transducer having a plurality of concentric elliptically shaped conductive fingers situated in one quadrant of an ellipse and mounted on a piezoelectric material. Upon the application of an excitation frequency to said transducer a low frequency surface wave will propagate along the major axis of the ellipse and a high frequency surface wave will propagate along the minor axis of the ellipse. Resonance will occur at a predetermined point on a line through the elliptically-shaped fingers and the focus of the ellipse.