Abstract: Integrated circuits with memory circuitry may include error detection circuitry and error correction circuitry. The error detection circuitry may be used to detect soft errors in the memory circuitry. The error detection circuitry may include logic gates that are used to perform parity checking. The error detection circuitry may have an interleaved structure to provide interleaved data bit processing, may have a tree structure to reduce logic gate delays, and may be pipelined to optimize performance. The memory circuitry may be loaded with interleaved parity check bits in conjunction with the interleaved structure to provide multi-bit error detection capability. The parity check bits may be precomputed using design tools or computed during device configuration. In response to detection of a memory error, the error correction circuitry may be used to scan desired portions of the memory circuitry and to correct the memory error.

Abstract: A phase-locked loop circuit includes phase detection circuitry to generate a first control signal based on a phase comparison between first and second periodic signals. An oscillator circuit causes a frequency of a third periodic signal to vary based on the first control signal. A frequency divider circuit divides the frequency of the third periodic signal by a frequency division value to generate a frequency of the second periodic signal. A delta sigma modulator circuit controls the frequency division value based on second control signals. First storage circuits store the second control signals based on third control signals in response to a fourth periodic signal. A second storage circuit stores an output signal based on a fourth control signal. The fourth periodic signal is generated based on the output signal of the second storage circuit.

Abstract: Integrated circuits with memory circuitry may include error detection circuitry and error correction circuitry. The error detection circuitry may be used to detect soft errors in the memory circuitry. The error detection circuitry may include logic gates that are used to perform parity checking. The error detection circuitry may have an interleaved structure to provide interleaved data bit processing, may have a tree structure to reduce logic gate delays, and may be pipelined to optimize performance. The memory circuitry may be loaded with interleaved parity check bits in conjunction with the interleaved structure to provide multi-bit error detection capability. The parity check bits may be precomputed using design tools or computed during device configuration. In response to detection of a memory error, the error correction circuitry may be used to scan desired portions of the memory circuitry and to correct the memory error.

Abstract: Techniques for sampling input data streams with an integrated circuit (IC) are provided. The technique includes receiving a first input stream at a first operating rate. The first input stream is transmitted to a plurality of subsequent transceiver channels on the IC. The first input stream is then sampled at a second operating rate at each of the plurality of subsequent transceiver channels with each of the plurality of subsequent transceiver channels outputting a data stream at the second operating rate. The data stream from each of the plurality of subsequent transceiver channels is adjusted. A data stream from one of the plurality of subsequent transceiver channels is selected as an output of the IC.

Abstract: A demultiplexer circuit separates input data having different data rates into output data. A phase-locked loop circuit generates first clock signals having average frequencies that are based on a frequency of a second clock signal times a fractional, non-integer number. A serializer circuit serializes a set of the output data to generate serial data signals in response to one of the first clock signals generated by the phase-locked loop circuit.

Abstract: A method to configure a programmable device is disclosed. The method includes receiving a scrambled configuration data at the programmable device. A bit sequence of a device tag that is stored in the programmable device is verified by determining whether the bit sequence of the device tag stored in the programmable device matches a bit sequence of a device tag within the scrambled configuration data. If the bit sequences match, the scrambled configuration data is transferred to a data re-formatter for descrambling. The descrambled configuration data is then transferred to a configuration memory of the programmable device. Circuitry that enables the method is also disclosed.

Abstract: Integrated circuits with memory circuitry may include error detection circuitry and error correction circuitry. The error detection circuitry may be used to detect soft errors in the memory circuitry. The error detection circuitry may include logic gates that are used to perform parity checking. The error detection circuitry may have an interleaved structure to provide interleaved data bit processing, may have a tree structure to reduce logic gate delays, and may be pipelined to optimize performance. The memory circuitry may be loaded with interleaved parity check bits in conjunction with the interleaved structure to provide multi-bit error detection capability. The parity check bits may be precomputed using design tools or computed during device configuration. In response to detection of a memory error, the error correction circuitry may be used to scan desired portions of the memory circuitry and to correct the memory error.

Abstract: A neuron for an artificial neural network provides digital weighting of input signals at a common portion of the neuron rather than at each synapse. The neuron is adapted for use of differential signals, and the weighting may be provided by field effect transistors of different widths, by subtracting a plurality of differential signal components from an opposite most significant component, or by subtracting one half of a differential signal component from the opposite next most significant component. The neuron may provide binary sign selection and digit selection by switching input and reference signals at each synapse.