Patents by Inventor Paul B. Hashimoto

Paul B. Hashimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatus and method for reducing the interface resistance in GaN Heterojunction FETs
    Patent number: 9252247
    Abstract: The interface resistance between the source/drain and gate of an HFET may be significantly reduced by engineering the bandgap of the 2DEG outside a gate region such that the charge density is substantially increased. The resistance may be further reduced by using an n+GaN Cap layer over the channel layer and barrier layer such that a horizontal surface of the barrier layer beyond the gate region is covered by the n+GaN Cap layer. This technique is applicable to depletion and enhancement mode HFETs.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: February 2, 2016
    Assignee: HRL Laboratories, LLC
    Inventors: Miroslav Micovic, Andrea Corrion, Keisuke Shinohara, Peter J Willadsen, Shawn D Burnham, Hooman Kazemi, Paul B Hashimoto
  • Self-aligned sidewall gate GaN HEMT
    Patent number: 8766321
    Abstract: A method of fabricating a GaN HEMT includes growing a first epitaxial layer on a substrate, growing a second epitaxial layer on the first epitaxial layer, growing a third epitaxial layer on the second epitaxial layer, depositing a first dielectric film on the third epitaxial layer, using dielectric films to form a first sidewall dielectric spacer, forming a sidewall gate adjacent the first sidewall dielectric spacer. The sidewall gate may be made to be less than 50 nm in length.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: July 1, 2014
    Assignee: HRL Laboratories, LLC
    Inventors: Keisuke Shinohara, Andrea Corrion, Miroslav Micovic, Paul B. Hashimoto, Shawn D. Burnham, Hooman Kazemi, Peter J. Willadsen, Dean C. Regan
  • Enhancement and depletion mode GaN HMETs on the same substrate
    Patent number: 8748244
    Abstract: The present invention relates to fabrication of enhancement mode and depletion mode High Electron Mobility Field Effect Transistors on the same die separated by as little as 10 nm. The fabrication method uses selective decomposition and selective regrowth of the Barrier layer and the Cap layer to engineer the bandgap of a region on a die to form an enhancement mode region. In these regions zero or more devices may be fabricated.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: June 10, 2014
    Assignee: HRL Laboratories, LLC
    Inventors: Andrea Corrion, Miroslav Micovic, Keisuke Shinohara, Peter J Willadsen, Shawn D Burnham, Hooman Kazemi, Paul B Hashimoto
  • Apparatus and method for reducing the interface resistance in GaN heterojunction FETs
    Patent number: 8686473
    Abstract: The interface resistance between the source/drain and gate of an HFET may be significantly reduced by engineering the bandgap of the 2DEG outside a gate region such that the charge density is substantially increased. The resistance may be further reduced by using an n+GaN Cap layer over the channel layer and barrier layer such that a horizontal surface of the barrier layer beyond the gate region is covered by the n+GaN Cap layer. This technique is applicable to depletion and enhancement mode HFETs.
    Type: Grant
    Filed: June 2, 2010
    Date of Patent: April 1, 2014
    Assignee: HRL Laboratories, LLC
    Inventors: Miroslav Micovic, Andrea Corrion, Keisuke Shinohara, Peter J Willadsen, Shawn D Burnham, Hooman Kazemi, Paul B Hashimoto
  • Self aligned sidewall gate GaN HEMT
    Patent number: 8383471
    Abstract: A method of fabricating a GaN HEMT includes growing a first epitaxial layer on a substrate, growing a second epitaxial layer on the first epitaxial layer, growing a third epitaxial layer on the second epitaxial layer, depositing a first dielectric film on the third epitaxial layer, using dielectric films to form a first sidewall dielectric spacer, forming a sidewall gate adjacent the first sidewall dielectric spacer. The sidewall gate may be made to be less than 50 nm in length.
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: February 26, 2013
    Assignee: HRL Laboratories, LLC
    Inventors: Keisuke Shinihara, Andrea Corrion, Miroslav Micovic, Paul B. Hashimoto, Shawn D. Burnham, Hooman Kazemi, Peter J. Willadsen, Dean C. Regan