Patents by Inventor Paul B. Kubista

Paul B. Kubista has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6813751
    Abstract: A method, a data structure, a computer program product and a computer for testing digital designs defining integrated circuits in a HDL before actually building the integrated circuits and, more specifically, for creating standard test environments for digital designs. One embodiment provides a method of creating an entity description for use in an automated testing environment, the entity description defining an entity of an integrated circuit in a hardware description language, the entity of the integrated circuit comprising at least one interface having a plurality of ports each associated with a pre-determined function. The method comprises, for at least one port of the plurality of ports, associating at least one indication of a specific procedure call with the at least one port, the specific procedure call defining the pre-determined function of the at least one port.
    Type: Grant
    Filed: July 16, 2002
    Date of Patent: November 2, 2004
    Assignee: International Business Machines Corporation
    Inventor: Paul B. Kubista
  • Patent number: 6721798
    Abstract: A method and apparatus is provided for an Ethernet station that transmits blocks of Ethernet frames in datagrams utilizing a pointer at the beginning of the datagram, rather than interrupts at the beginning and end of each data frame. Hardware receives a pointer to the start of an IP datagram and is then prompted to transmit. Hardware forms the frame header and sends out the IP datagram as a series of frames with only one interrupts signaling the end of the datagram. As a transmission comes in to the receiving station, hardware will check first to see if this is part of an IP datagram currently being received. If not, the frame is stored in a new location. If it is part of a datagram that is currently being received, hardware will check an offset in the IP header to determine where the new frame should be placed so the IP datagram is assembled properly.
    Type: Grant
    Filed: May 6, 1999
    Date of Patent: April 13, 2004
    Assignee: International Business Machines Corporation
    Inventor: Paul B. Kubista
  • Publication number: 20040015792
    Abstract: A method, a data structure, a computer program product and a computer for testing digital designs defining integrated circuits in a HDL before actually building the integrated circuits and, more specifically, for creating standard test environments for digital designs. One embodiment provides a method of creating an entity description for use in an automated testing environment, the entity description defining an entity of an integrated circuit in a hardware description language, the entity of the integrated circuit comprising at least one interface having a plurality of ports each associated with a pre-determined function. The method comprises, for at least one port of the plurality of ports, associating at least one indication of a specific procedure call with the at least one port, the specific procedure call defining the pre-determined function of the at least one port.
    Type: Application
    Filed: July 16, 2002
    Publication date: January 22, 2004
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Paul B. Kubista
  • Patent number: 6658519
    Abstract: A transaction tracing circuit for use with a bus bridge that is couplable to at least a first and second bus. The transaction tracing circuit includes at least one set of trace control registers that is associated with a transaction tracing function for tracing a specific transaction occurring on the bus bridge. A number of bus transaction tracing circuits, one for each bus to which the bridge is connected, are coupled to the trace control registers and are utilized to store is transactions that are captured as they occur on the individual buses. An internal transaction tracing circuit is coupled to the trace control registers and is utilized for storing captured internal transaction information corresponding to the specific internal transaction.
    Type: Grant
    Filed: July 28, 2000
    Date of Patent: December 2, 2003
    Assignee: International Business Machines Corporation
    Inventors: Robert Neal Broberg, III, Paul B. Kubista, Daniel Frank Moertl, Daniel Paul Wetzel
  • Patent number: 6381648
    Abstract: Within a communication node, low level hardware is programmed and provided with filter data to accept broadcast frames. A high level layer of hardware, utilizing the pre-loaded, pre-defined comparison data, checks incoming frame header information. Based on pre-defined filter data or reference values loaded into low level registers, the high-level hardware will reject or accept submitted data communication frames. This method reduces the requirement for software to operate on each incoming frame header, thus reducing load on the processor.
    Type: Grant
    Filed: May 6, 1999
    Date of Patent: April 30, 2002
    Assignee: International Business Machines Corporation
    Inventors: Robert Neal Carlton Broberg, III, Paul B. Kubista, Gerald David Miller