Patents by Inventor Paul B. Patterson

Paul B. Patterson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Voltage mode sensing for low power flash memory
    Patent number: 9607708
    Abstract: Electrically erasable flash memory and method. The memory has a data storage element and a voltage sensing circuit. The data storage element is configured to store data bits, each of the data bits having a data state. The voltage sensing circuit is selectively coupled to individual ones of data bits and is configured to bias the data bits with at least one of a bias current and a bias resistance and to read the data state of the individual ones of the plurality of data bits.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: March 28, 2017
    Assignee: Medtronic, Inc.
    Inventors: Kevin K. Walsh, Paul B. Patterson, Glen W. Benton, Jeffrey D. Wilkinson
  • Flash memory with integrated ROM memory cells
    Patent number: 9053791
    Abstract: Memory array for storing a plurality of data bits. The memory array has flash memory cells, ROM memory cells addressing circuitry. The addressing circuitry is operatively coupled to both the plurality of flash memory cells and the plurality of ROM memory cells, the addressing circuitry being configured to address both the plurality of flash memory cells and the plurality of ROM memory cells.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: June 9, 2015
    Assignee: Medtronic, Inc.
    Inventors: Kevin K. Walsh, Paul B. Patterson, Glen W. Benton, Jeffrey D. Wilkinson
  • VOLTAGE MODE SENSING FOR LOW POWER FLASH MEMORY
    Publication number: 20130235663
    Abstract: Electrically erasable flash memory and method. The memory has a data storage element and a voltage sensing circuit. The data storage element is configured to store data bits, each of the data bits having a data state. The voltage sensing circuit is selectively coupled to individual ones of data bits and is configured to bias the data bits with at least one of a bias current and a bias resistance and to read the data state of the individual ones of the plurality of data bits.
    Type: Application
    Filed: October 31, 2012
    Publication date: September 12, 2013
    Applicant: MEDTRONIC, INC.
    Inventors: Kevin K. Walsh, Paul B. Patterson, Glen W. Benton, Jeffrey D. Wilkinson
  • FLASH MEMORY WITH INTEGRATED ROM MEMORY CELLS
    Publication number: 20130235672
    Abstract: Memory array for storing a plurality of data bits. The memory array has flash memory cells, ROM memory cells addressing circuitry. The addressing circuitry is operatively coupled to both the plurality of flash memory cells and the plurality of ROM memory cells, the addressing circuitry being configured to address both the plurality of flash memory cells and the plurality of ROM memory cells.
    Type: Application
    Filed: October 31, 2012
    Publication date: September 12, 2013
    Applicant: Medtronic, Inc.
    Inventors: Kevin K. Walsh, Paul B. Patterson, Glen W. Benton, Jeffrey D. Wilkinson