Abstract: Systems and methods for executing program instructions in a data processor at a variable rate. In one embodiment, a processor is configured to examine received instructions, identify an execution time associated with each instruction, and generate clock pulses at necessary intervals to obtain the appropriate execution time for each instruction. Instructions may be associated with types or “bins” that are in turn associated with corresponding execution times. The clock pulses may be generated by routing successive pulses through circuits that delay the pulses by desired amounts of time. The processor may also be configured to identify instructions which are input/output (I/O) instructions and are initiated or terminated by completion of handshake procedures and therefore have execution times that vary from one instance to the next.

Abstract: Systems and methods for processing data using an array of data processing elements that are coupled together with a variable precision interconnect. One embodiment comprises data processing elements coupled by variable precision interconnects to form a row-column array. The interconnects and/or data processing elements may be synchronous or asynchronous. The data processing elements may operate in a fixed manner, or they may be programmable, and selectable data processing elements in the array may be bypassed. The interconnects and data processing elements may be configured to handle data in a digit-serial manner, with tags for each digit identifying whether the digit is the first and/or last digit in a data word. The data processing elements may be coupled to a system bus that enables communication of data between the data processing elements and external devices and allows control information to be communicated to and from the data processing elements.

Abstract: A system and method for providing sound in a computer are disclosed. An audio module for controlling digitized sound I/O is included in a media stream controller. The media stream controller may also coordinate graphics and video which allows multiple media subsystems to be supported from a single bus device. A software application may initiate sound data transfer by sending a conventional DMA mode command to the media stream controller. The media stream controller activates an audio interrupt service routine which processes the request without using a conventional DMA controller. Digital sound data is transferred across a local bus using high speed burst mode block transfer commands and is buffered by the media stream controller in a display memory. Concurrently, the media stream controller may output sound data from the display memory to a sound output device using a double buffering method.

Abstract: Multimedia information (e.g. graphics, video, sound, control information) passes through a system bus from a CPU main memory to a display memory in accordance with CPU commands. The information may be packetized with associated packet types identifying the different media. A media stream controller processes the information and passes the processed information to the display memory. Controllers in the media stream controller individually pass multimedia information to the display memory. A PACDAC controller in the media stream controller causes media (e.g. graphics, video) in the display memory to be transferred to a PACDAC for display. The format, sequence, and rate of this transfer may be flexibly controlled by software on a frame by frame basis. Arbitration logic establishes priorities for the different controllers in the media stream controller so they may share a single bus for accessing the display memory. A single interrupt controller coordinates interrupts (e.g.

Abstract: Aspects of the present invention provide a system for selectively processing a video signal in accordance with instructions from application software. The system contains a video decoder for converting an analog video signal to digital video data, and a controller for formatting and routing the digital video data. A list of control structures may be loaded into a memory associated with the controller. The control structures contain formatting and routing information used by the controller to process different portions of the video stream. The number and content of control structures as well as the correlation between the control structures and selected portions of the video stream may be flexibly determined by application software. In particular, the control structures may be configured such that certain portions of the video stream are routed to the CPU for processing, while other portions are routed to a display driver and output on a display device.

Abstract: A graphics subsystem, including a video digital-to-analog converter, is disclosed. A high speed oscillator generates a pixel clock signal at the frequency at which pixels are to be displayed. Included in the video DAC is a frequency divider which presents an output clock signal having a period which is a multiple of the pixel clock signal, the multiple corresponding to the level of multiplexing of pixel data to be provided by the video DAC; this multiple can equal unity. The video controller in the system receives the output clock signal, and generates clock signals to control the serial port of the frame memory, and also to control the latching of the first stage in the video DAC. The first stage latch in the video DAC latches in the multiple pixel data from the frame memory, and the multiplexer in the video DAC presents the data to the color palette RAM, or around the color palette RAM in true-color non-multiplexed mode, according to the pixel clock signal.

Abstract: A method and apparatus for making wire harness. The apparatus includes the use of a sequential wire processor that serially and sequentially fabricates circuits having terminal ends. The terminated circuits are transferred by a transfer means to an upstanding carousel provided with arrays of circuit-receiving clips. The transfer means receives terminated circuits from the sequential wire processor and places them on the clips of the carousel. The carousel is then moved to an assembly line and robotic station where robots remove the circuits from the clips of the carousel and place the terminated ends of the circuits in cavities of connectors strategically located on the assembly line. The robots have end effectors that physically insert the terminal ends into the connector cavities.

Abstract: A system and method for providing sound in a computer are disclosed. An audio module for controlling digitized sound I/O is included in a media stream controller. The media stream controller may also coordinate graphics and video which allows multiple media subsystems to be supported from a single bus device. A software application may initiate sound data transfer by sending a conventional DMA mode command to the media stream controller. The media stream controller activates an audio interrupt service routine which processes the request without using a conventional DMA controller. Digital sound data is transferred across a local bus using high speed burst mode block transfer commands and is buffered by the media stream controller in a display memory. Concurrently, the media stream controller may output sound data from the display memory to a sound output device using a double buffering method.

Abstract: Line draw circuitry receives parameters defining first and second endpoints of a line and calculates line parameters based on the first and second endpoints. The line parameters are then stored in a memory. A "calculate-only" control signals determines whether a line is drawn immediately after calculation (and storing) of the end parameters or whether the line is drawn responsive to a subsequent "start" signal. If the line is to be drawn responsive to the start signal, the line parameters may be modified prior to drawing the line.

Abstract: A graphics processor uses a line draw facility to receive first and second values indicative of the coordinates of respective first and second end points of a line. The reception of the second value is sensed by the line draw facility and line data is generated responsive to the sensing of the second value.

Abstract: A graphics subsystem, including a video digital-to-analog converter, is disclosed. A high speed oscillator generates a pixel clock signal at the frequency at which pixels are to be displayed. Included in the video DAC is a frequency divider which presents an output clock signal having a period which is a multiple of the pixel clock signal, the multiple corresponding to the level of multiplexing of pixel data to be provided by the video DAC; this multiple can equal unity. The video controller in the system receives the output clock signal, and generates clock signals to control the serial port of the frame memory, and also to control the latching of the first stage in the video DAC. The first stage latch in the video DAC latches in the multiple pixel data from the frame memory, and the multiplexer in the video DAC presents the data to the color palette RAM, or around the color palette RAM in true-color non-multiplexed mode, according to the pixel clock signal.

Abstract: A method and apparatus for making wire harness. The apparatus includes the use of a sequential wire processor that serially and sequentially fabricates circuits having terminal ends. The terminated circuits are transferred by a transfer means to an upstanding carousel provided with arrays of circuit-receiving clips. The transfer means receives terminated circuits from the sequential wire processor and places them on the clips of the carousel. The carousel is then moved to an assembly line and robotic station where robots remove the circuits from the clips of the carousel and place the terminated ends of the circuits in cavities of connectors strategically located on the assembly line. The robots have end effectors that physically insert the terminal ends into the connector cavities.

Abstract: A graphics subsystem, including a video digital-to-analog converter, is disclosed. A high speed oscillator generates a pixel clock signal at the frequency at which pixels are to be displayed. Included in the video DAC is a frequency divider which presents an output clock signal having a period which is a multiple of the pixel clock signal, the multiple corresponding to the level of multiplexing of pixel data to be provided by the video DAC; this multiple can equal unity. The video controller in the system receives the output clock signal, and generates clock signals to control the serial port of the frame memory, and also to control the latching of the first stage in the video DAC. The first stage latch in the video DAC latches in the multiple pixel data from the frame memory, and the multiplexer in the video DAC presents the data to the color palette RAM, or around the color palette RAM in true-color non-multiplexed mode, according to the pixel clock signal.

Abstract: A graphics subsystem, including a video digital-to-analog converter, is disclosed. A high speed oscillator generates a pixel clock signal at the frequency at which pixels are to be displayed. Included in the video DAC is a frequency divider which presents an output clock signal having a period which is a multiple of the pixel clock signal, the multiple corresponding to the level of multiplexing of pixel data to be provided by the video DAC; this multiple can equal unity. The video controller in the system receives the output clock signal, and generates clock signals to control the serial port of the frame memory, and also to control the latching of the first stage in the video DAC. The first stage latch in the video DAC latches in the multiple pixel data from the frame memory, and the multiplexer in the video DAC presents the data to the color palette RAM, or around the color palette RAM in true-color non-multiplexed mode, according to the pixel clock signal.

Abstract: A graphics subsystem, including a video digital-to-analog converter, is disclosed. A high speed oscillator generates a pixel clock signal at the frequency at which pixels are to be displayed. Included in the video DAC is a frequency divider which presents an output clock signal having a period which is a multiple of the pixel clock signal, the multiple corresponding to the level of multiplexing of pixel data to be provided by the video DAC; this multiple can equal unity. The video controller in the system receives the output clock signal, and generates clock signals to control the serial port of the frame memory, and also to control the latching of the first stage in the video DAC. The first stage latch in the video DAC latches in the multiple pixel data from the frame memory, and the multiplexer in the video DAC presents the data to the color palette RAM, or around the color palette RAM in true-color non-multiplexed mode, according to the pixel clock signal.

Abstract: A data display and management system includes a microprocessor whose functions are implemented by instructions in data from a directly connected main memory. A mass data storage memory is connected to the main memory and has permanently stored instructions therein for the microprocessor. A display control system which operates asynchronously with the microprocessor includes a display controller, display memory, character memory means, and a visual character attribute generator. By linking one or more row attribute bytes, or pointers, to each row of characters stored in the display memory the display controller performs character and row manipulation on a display device without transferring whole blocks of data in the display memory. Multi-region display segmentation into horizontal and vertical split regions, smooth or discrete scrolling of individual regions, and various editing functions are achieved by modifying the associated display memory pointers.

Abstract: A display control system which operates asynchronously with a microprocessor includes a display controller, display memory, character memory means, and a visual character attribute generator. By linking one or more row attribute bytes, or pointers, to each row of characters stored in the display memory the display controller performs character and row manipulation on a display device without transferring whole blocks of data in the display memory. Multi-region display segmentation into horizontal and vertical split regions, smooth or discrete scrolling of individual regions, and various editing functions are achieved by modifying the associated display memory pointers. In one embodiment the display controller is a single integrated circuit device.